公开(公告)号：US20230066610A1

公开(公告)日：2023-03-02

申请号：US17411599

申请日：2021-08-25

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

IPC: H01L23/00

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

公开(公告)号：US11437488B2

公开(公告)日：2022-09-06

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/203 ,  H01L21/8234 ,  H01L29/423

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

公开(公告)号：US11798982B2

公开(公告)日：2023-10-24

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L21/761 ,  H01L21/7602 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

公开(公告)号：US20220344453A1

公开(公告)日：2022-10-27

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

公开(公告)号：US12033964B2

公开(公告)日：2024-07-09

申请号：US17411599

申请日：2021-08-25

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/7684 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/03616 ,  H01L2224/05073 ,  H01L2224/05647 ,  H01L2224/27616 ,  H01L2224/29186

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

公开(公告)号：US20220165863A1

公开(公告)日：2022-05-26

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/203

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.