公开(公告)号：US20240255700A1

公开(公告)日：2024-08-01

申请号：US18102927

申请日：2023-01-30

Applicant: Applied Materials, Inc.

Inventor： Eric Jay Simmons ,  Qintao Zhang ,  Wei Zou ,  Andrew Michael Waite ,  Jared Forrest Traynor ,  Miguel Sam Fung ,  Vincent V. Granuzzo ,  David J. Lee

IPC: G02B6/134 ,  H01L27/144

CPC classification number: G02B6/1347 ,  H01L27/1443

Abstract: Disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. One method includes providing a workpiece including a contact etch stop layer (CESL) over a device layer, patterning the CESL to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. The method may further include directing ions into an upper surface of the waveguide using a high-temperature ion implant to decrease a surface roughness of the upper surface of the waveguide.

公开(公告)号：US20240128131A1

公开(公告)日：2024-04-18

申请号：US17966634

申请日：2022-10-14

Applicant: Applied Materials, Inc.

Inventor： Avishay Vaxman ,  Qintao Zhang ,  Jeffrey P. Koch ,  David P. Surdock ,  Wayne R. Swart ,  David J. Lee ,  Samphy Hong ,  Aldrin Bernard Vincent Eddy ,  Daniel G. Deyo

IPC: H01L21/66 ,  G06T7/00 ,  G06T7/80 ,  H04N5/225 ,  H04N5/232

CPC classification number: H01L22/24 ,  G06T7/001 ,  G06T7/80 ,  H01L22/26 ,  H04N5/2256 ,  H04N5/23222 ,  H04N5/23229 ,  G06T2207/30148

Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

公开(公告)号：US11695060B2

公开(公告)日：2023-07-04

申请号：US17127298

申请日：2020-12-18

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Lei Zhong ,  David J. Lee ,  Felix Levitov

IPC: H01L21/04 ,  H01L21/28 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66734 ,  H01L21/2822 ,  H01L29/42368

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

公开(公告)号：US20220415656A1

公开(公告)日：2022-12-29

申请号：US17358244

申请日：2021-06-25

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Vittoriano Ruscio ,  Wei Zou ,  David J. Lee

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US12046473B2

公开(公告)日：2024-07-23

申请号：US17358244

申请日：2021-06-25

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Vittoriano Ruscio ,  Wei Zou ,  David J. Lee

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L21/265 ,  H01L21/26593 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US11437488B2

公开(公告)日：2022-09-06

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/203 ,  H01L21/8234 ,  H01L29/423

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

公开(公告)号：US20220165863A1

公开(公告)日：2022-05-26

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/203

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

公开(公告)号：US11798982B2

公开(公告)日：2023-10-24

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L21/761 ,  H01L21/7602 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

公开(公告)号：US11527412B2

公开(公告)日：2022-12-13

申请号：US17113073

申请日：2020-12-06

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Felix Levitov ,  Lei Zhong ,  Wei Zou

IPC: H01L21/311 ,  H01J37/317 ,  H01L21/3115

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

公开(公告)号：US20220344453A1

公开(公告)日：2022-10-27

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.