公开(公告)号：US20170309525A1

公开(公告)日：2017-10-26

申请号：US15492428

申请日：2017-04-20

Applicant: Applied Materials, Inc.

Inventor： Yoichi SUZUKI ,  Michael Wenyoung TSIANG ,  Kwangduk Douglas LEE ,  Takashi MORII ,  Yuta GOTO

IPC: H01L21/66 ,  H01L21/67 ,  C23C16/50 ,  H01L21/324 ,  H01L21/02 ,  C23C16/56 ,  C23C16/52 ,  H01L21/677

CPC classification number: H01L22/20 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/324 ,  H01L21/67098 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67742 ,  H01L22/12

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.

公开(公告)号：US20180226306A1

公开(公告)日：2018-08-09

申请号：US15944830

申请日：2018-04-04

Applicant: Applied Materials, Inc.

Inventor： Yoichi SUZUKI ,  Michael Wenyoung TSIANG ,  Kwangduk Douglas LEE ,  Takashi MORII ,  Yuta GOTO

IPC: H01L21/66 ,  H01L21/67 ,  C23C16/46 ,  H01L21/324 ,  H01L21/02 ,  C23C16/50 ,  C23C16/56 ,  H01L21/677 ,  C23C16/52

CPC classification number: H01L22/20 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/324 ,  H01L21/67098 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67742 ,  H01L22/12

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.