公开(公告)号：US20150138901A1

公开(公告)日：2015-05-21

申请号：US14083619

申请日：2013-11-19

Applicant: Arm Limited

Inventor： Andy Wangkun CHEN ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C7/12 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

公开(公告)号：US20160180896A1

公开(公告)日：2016-06-23

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus YEUNG ,  Fakhruddin Ali BOHRA ,  Mudit BHARGAVA ,  Andy Wangkun CHEN ,  Yew Keong CHONG

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract translation: 存储器2包括存储元件4的规则阵列。写入多路复用器8的规则阵列被提供在存储元件4的规则阵列之外。存储元件间距与写多路复用器间距匹配。 写多路复用器10支持多个写端口。 当形成存储器设计2时，可以根据要支持的写入端口的期望数量来选择写入多路复用器8的阵列的给定实例，并且与常规形式的存储元件阵列4组合。