公开(公告)号：US20240249790A1

公开(公告)日：2024-07-25

申请号：US18100614

申请日：2023-01-24

Applicant: Arm Limited

Inventor： Yannis Jallamion-Grive ,  Yunpeng Cai ,  Mohammed Adnan Addou ,  Anil Kumar Baratam ,  Denil Das Kolady ,  Chandru Tavarekere Krishnegowda ,  Jad Mohdad ,  Yves Thomas Laplanche ,  Yannick Marc Nevers

IPC: G11C29/30 ,  G11C29/12

CPC classification number: G11C29/30 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/3202

Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.