公开(公告)号：US20240249790A1

公开(公告)日：2024-07-25

申请号：US18100614

申请日：2023-01-24

Applicant: Arm Limited

Inventor： Yannis Jallamion-Grive ,  Yunpeng Cai ,  Mohammed Adnan Addou ,  Anil Kumar Baratam ,  Denil Das Kolady ,  Chandru Tavarekere Krishnegowda ,  Jad Mohdad ,  Yves Thomas Laplanche ,  Yannick Marc Nevers

IPC: G11C29/30 ,  G11C29/12

CPC classification number: G11C29/30 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/3202

Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.

公开(公告)号：US08941428B2

公开(公告)日：2015-01-27

申请号：US14248555

申请日：2014-04-09

Applicant: ARM Limited

Inventor： Virgile Javerliac ,  Yannick Marc Nevers ,  Laurent Christian Sibuet ,  Selma Laabidi

IPC: H03K3/289 ,  H03K3/037 ,  G11C11/412 ,  G11C19/28 ,  H03K3/012

CPC classification number: H03K3/037 ,  G11C11/412 ,  G11C19/28 ,  H03K3/012 ,  H03K3/0372

Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.

Abstract translation: 锁存电路具有用于接收数据值的输入，用于输出表示数据值的值的输出，用于接收时钟信号的时钟信号输入; 和通行证。 反馈回路具有并联布置在两个反相器件之间的两个开关电路，两个开关电路中的第一个被配置为截止并且不响应于具有预定控制值的控制信号而导通，并且两个开关电路中的第二个是 被配置为接通并响应于具有预定控制值的控制信号而导通。 控制两个开关电路的控制信号被链接，使得开关装置切换其导通状态，并且访问控制装置一起起作用以更新反馈回路内的数据值。

公开(公告)号：US20240260261A1

公开(公告)日：2024-08-01

申请号：US18103316

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Yannick Marc Nevers ,  Valerio Lanieri ,  Amit Chhabra

IPC: H10B20/00

CPC classification number: H10B20/50 ,  H10B20/34

Abstract: Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.

公开(公告)号：US10558585B2

公开(公告)日：2020-02-11

申请号：US15355785

申请日：2016-11-18

Applicant: ARM Limited

Inventor： Yannick Marc Nevers ,  Bastien Jean Claude Aghetti ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Stephane Zonza

IPC: G06F12/14 ,  G06F21/79 ,  G06F12/1009 ,  G06F21/55

Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.