公开(公告)号：US09985613B2

公开(公告)日：2018-05-29

申请号：US15336721

申请日：2016-10-27

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

公开(公告)号：US11569824B2

公开(公告)日：2023-01-31

申请号：US17344390

申请日：2021-06-10

Applicant: Arm Limited

Inventor： Shidhartha Das ,  Yunpeng Cai ,  Supreet Jeloka

IPC: H03L7/099 ,  H03L7/187 ,  H03L7/091 ,  H03L7/199 ,  H03L7/081

Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

公开(公告)号：US20240249790A1

公开(公告)日：2024-07-25

申请号：US18100614

申请日：2023-01-24

Applicant: Arm Limited

Inventor： Yannis Jallamion-Grive ,  Yunpeng Cai ,  Mohammed Adnan Addou ,  Anil Kumar Baratam ,  Denil Das Kolady ,  Chandru Tavarekere Krishnegowda ,  Jad Mohdad ,  Yves Thomas Laplanche ,  Yannick Marc Nevers

IPC: G11C29/30 ,  G11C29/12

CPC classification number: G11C29/30 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/3202

Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.

公开(公告)号：US20180123571A1

公开(公告)日：2018-05-03

申请号：US15336721

申请日：2016-10-27

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

公开(公告)号：US20220399895A1

公开(公告)日：2022-12-15

申请号：US17344390

申请日：2021-06-10

Applicant: Arm Limited

Inventor： Shidhartha Das ,  Yunpeng Cai ,  Supreet Jeloka

IPC: H03L7/099 ,  H03L7/187 ,  H03L7/081 ,  H03L7/199 ,  H03L7/091

Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

公开(公告)号：US20180278244A1

公开(公告)日：2018-09-27

申请号：US15990538

申请日：2018-05-25

Applicant: ARM Limited ,  University of Southampton

Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

IPC: H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/35625 ,  H03K19/20

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.