公开(公告)号：US20250015133A1

公开(公告)日：2025-01-09

申请号：US18219292

申请日：2023-07-07

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Dileep Choorakuzhi Ramakrishnan ,  Subramanya Ravindra Shindagikar ,  Ala Srinivasa Rao

IPC: H01L29/06 ,  G06F30/392 ,  H01L27/092 ,  H01L29/78

Abstract: Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.

公开(公告)号：US11900039B2

公开(公告)日：2024-02-13

申请号：US17175639

申请日：2021-02-13

Applicant: Arm Limited

Inventor： Anil Kumar Baratam, Jr. ,  Subramanya Ravindra Shindagikar

IPC: G06F30/39 ,  G11C7/10 ,  H03K19/21 ,  G11C11/40

CPC classification number: G06F30/39 ,  G11C7/10 ,  G11C11/40 ,  H03K19/21

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

公开(公告)号：US10922465B2

公开(公告)日：2021-02-16

申请号：US16144688

申请日：2018-09-27

Applicant: Arm Limited

Inventor： Anil Kumar Baratam ,  Subramanya Ravindra Shindagikar

IPC: G06F30/39 ,  G11C7/10 ,  H03K19/21 ,  G11C11/40

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

公开(公告)号：US20210165945A1

公开(公告)日：2021-06-03

申请号：US17175639

申请日：2021-02-13

Applicant: Arm Limited

Inventor： Anil Kumar Baratam, JR. ,  Subramanya Ravindra Shindagikar

IPC: G06F30/39 ,  H03K19/21 ,  G11C7/10 ,  G11C11/40

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.