公开(公告)号：US06404019B1

公开(公告)日：2002-06-11

申请号：US09676870

申请日：2000-09-29

申请人： Armin M. Reith ,  Tina Leidinger ,  Gunther Lehmann

发明人： Armin M. Reith ,  Tina Leidinger ,  Gunther Lehmann

IPC分类号： H01L2994

CPC分类号： G11C7/065 ,  H01L27/10897

摘要： A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.

摘要翻译： 在硅集成电路中形成用于动态随机存取存储器的读出放大器。 这种读出放大器的阵列的间距等于存储器阵列的位线对的间距。 每个读出放大器阵列由具有U形栅电极的给定n或p沟道型金属氧化物半导体（MOS）晶体管的四行晶体管形成。 读出放大器的每行晶体管中的晶体管的栅电极以预先选定的量偏离前一行。 通过读出放大器的位线是直的，没有偏移影响光刻性能，也没有突起增加位线的电容。 这种读出放大器阵列的尺寸等于位线对的最小尺寸，因此不会导致存储器单元阵列的宽度的任何增加。

公开(公告)号：US06353248B1

公开(公告)日：2002-03-05

申请号：US09562220

申请日：2000-04-28

申请人： Armin M Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

发明人： Armin M Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

IPC分类号： H01L2976

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

摘要翻译： 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上的所有剩余空间都由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：US06232154B1

公开(公告)日：2001-05-15

申请号：US09442890

申请日：1999-11-18

申请人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

发明人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

IPC分类号： H01L2182

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

摘要翻译： 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：US08143694B2

公开(公告)日：2012-03-27

申请号：US12131134

申请日：2008-06-02

申请人： Vianney Choserot ,  Gunther Lehmann ,  Franz Ungar

发明人： Vianney Choserot ,  Gunther Lehmann ,  Franz Ungar

IPC分类号： H01L23/52

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.

摘要翻译： 本文提供了与保险丝装置，包括熔丝装置的集成电路，实现熔丝装置的方法和编程熔丝装置的方法相关的实施方式。

公开(公告)号：US07633787B2

公开(公告)日：2009-12-15

申请号：US11661582

申请日：2005-08-18

申请人： Siddarth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

发明人： Siddarth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

IPC分类号： G11C17/00

CPC分类号： G11C17/12 ,  G11C2207/2227

摘要： The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.

摘要翻译： 本发明涉及一种ROM存储单元，包括连接到字线的第一端子，包括第二端子并包括第三端子，第二端子连接到位线和/或第三端子连接到电源线 预充电第三个终端。 根据本发明的ROM存储器单元的特征在于，在待机操作模式中，相同的参考电位在每种情况下都应用于第一端子，第二端子和/或第三端子。 本发明还涉及一种包括这种ROM存储器单元的ROM存储器组件，以及一种用于从ROM存储单元读取的方法。

公开(公告)号：US07403432B2

公开(公告)日：2008-07-22

申请号：US11358374

申请日：2006-02-21

申请人： Gunther Lehmann ,  Vianney Choserot ,  Jean-Yves Larguier

发明人： Gunther Lehmann ,  Vianney Choserot ,  Jean-Yves Larguier

IPC分类号： G11C7/10

CPC分类号： G11C7/062 ,  G11C17/18

摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.

摘要翻译： 公开了一种读出电路，其中电路从包括两个非易失性存储器单元的存储器单元中读出信息。 单元具有不同的编程状态，并且存储器单元的存储器信息由两个存储器单元的编程状态给出。 读出电路具有易失性信号存储器，其输入连接到存储器单元的读取输出。

公开(公告)号：US20070121400A1

公开(公告)日：2007-05-31

申请号：US11528079

申请日：2006-09-26

申请人： Gunther Lehmann ,  Yannick Martelloni ,  Devesh Dwivedi ,  Siddharth Gupta

发明人： Gunther Lehmann ,  Yannick Martelloni ,  Devesh Dwivedi ,  Siddharth Gupta

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.

摘要翻译： 一种方法向存储器件的位线提供电压。 该方法包括使用预充电装置将位线预充电到输出电位，在与位线有关的读取动作期间停用预充电装置，在读取动作期间通过位线读取信息，以及在路线期间进行路由 读取动作，将虚拟电压提供到存储器件的电源电位，以将电压提供给分配给位线的存储器件的存储器单元。 作为虚拟电压供给线的电位的函数，位线的预充电装置被激活/去激活。

公开(公告)号：US20060203585A1

公开(公告)日：2006-09-14

申请号：US11358374

申请日：2006-02-21

申请人： Gunther Lehmann ,  Vianney Choserot ,  Jean-Yves Larguier

发明人： Gunther Lehmann ,  Vianney Choserot ,  Jean-Yves Larguier

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C17/18

摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells (F2, F3). The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells (F2, F3). The read-out circuit has a volatile signal memory (INV4, INV5), the inputs of which are connected to the read outputs of the memory cells (F2, F3).

摘要翻译： 公开了一种读出电路，其中电路从包括两个非易失性存储单元（F 2，F 3）的存储单元中读出信息。 单元具有不同的编程状态，存储单元的存储器信息由两个存储单元（F 2，F 3）的编程状态给出。 读出电路具有易失性信号存储器（INV 4，INV 5），其输入端连接到存储单元（F 2，F 3）的读出端。

公开(公告)号：US06603694B1

公开(公告)日：2003-08-05

申请号：US10068789

申请日：2002-02-05

申请人： Gerd Frankowsky ,  Gunther Lehmann

发明人： Gerd Frankowsky ,  Gunther Lehmann

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.

摘要翻译： 提供了用于刷新存储在动态存储单元阵列中的数据的电路。 该电路包括集成电路芯片。 芯片具有形成在其上的存储单元阵列。 该电路还包括用于确定每个存储器单元中的数据保持时间的刷新率分析电路，以及这些确定刷新地址修改信号。 还提供了一种刷新地址生成器，其形成在芯片上并由芯片外部产生的刷新命令信号和地址修改信号馈送。 刷新地址生成器向内存单元阵列提供内部刷新命令以及刷新地址。 小区具有响应于这种内部刷新命令刷新的数据。 刷新率分析电路确定具有小于预定值的数据保留时间的阵列中的单元。

公开(公告)号：US06549063B1

公开(公告)日：2003-04-15

申请号：US10044470

申请日：2002-01-11

申请人： Gunther Lehmann ,  Ulrich Frey

发明人： Gunther Lehmann ,  Ulrich Frey

IPC分类号： H01H3776

CPC分类号： H01L23/5256 ,  G01R31/07 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged with a predetermined voltage and/or current and the anti-fuse is subsequently evaluated. In one embodiment a precharge voltage sufficient to turn ON a transistor is provided to the gate. Here, an intact (unblown) transistor remains ON over a period of time and a damaged (blown) transistor dissipates the charge voltage and turns OFF. The status of the transistor is subsequently determined by evaluating the resistance between the drain and source. A high resistance indicates a blown condition and a low resistance indicates an unblown condition. In another embodiment, a small current is provided to the gate in which the small current is greater than a leakage current for an intact transistor and is less than a leakage current for a damaged transistor. An intact transistor charges to an ON state over a period of time but a damaged transistor does not because it's leakage current is greater than the small current provided to the gate. Again, the status of the transistor anti-fuse is subsequently determined by evaluating the resistance between the drain and source.

摘要翻译： 本发明提供了一种可编程反熔丝元件的评估。 对于可编程晶体管反熔丝，反熔丝的栅极以预定的电压和/或电流进行预充电，并且随后评估反熔丝。 在一个实施例中，向栅极提供足以导通晶体管的预充电电压。 这里，一个完整的（未吹制的）晶体管在一段时间内保持导通，并且损坏的（熔断）晶体管消耗充电电压并且关断。 随后通过评估漏极和源极之间的电阻来确定晶体管的状态。 高电阻表示吹出状态，低电阻表示未吹出状态。 在另一个实施例中，小电流被提供给栅极，其中小电流大于完整晶体管的漏电流，并且小于损坏晶体管的漏电流。 完整的晶体管在一段时间内充电到ON状态，但损坏的晶体管不是因为其漏电流大于提供给栅极的小电流。 再次，晶体管反熔丝的状态随后通过评估漏极和源极之间的电阻来确定。