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公开(公告)号：US20070121400A1
公开(公告)日：2007-05-31
申请号：US11528079
申请日：2006-09-26
IPC分类号： G11C7/00
摘要： A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.
摘要翻译： 一种方法向存储器件的位线提供电压。 该方法包括使用预充电装置将位线预充电到输出电位，在与位线有关的读取动作期间停用预充电装置，在读取动作期间通过位线读取信息，以及在路线期间进行路由 读取动作，将虚拟电压提供到存储器件的电源电位，以将电压提供给分配给位线的存储器件的存储器单元。 作为虚拟电压供给线的电位的函数，位线的预充电装置被激活/去激活。
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公开(公告)号：US07436721B2
公开(公告)日：2008-10-14
申请号：US11528079
申请日：2006-09-26
IPC分类号： G11C7/00
摘要： A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.
摘要翻译： 一种方法向存储器件的位线提供电压。 该方法包括使用预充电装置将位线预充电到输出电位，在与位线有关的读取动作期间停用预充电装置，在读取动作期间通过位线读取信息，以及在路线期间进行路由 读取动作，将虚拟电压提供到存储器件的电源电位，以将电压提供给分配给位线的存储器件的存储器单元。 作为虚拟电压供给线的电位的函数，位线的预充电装置被激活/去激活。
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公开(公告)号：US07366002B2
公开(公告)日：2008-04-29
申请号：US11267491
申请日：2005-11-04
IPC分类号： G11C17/00
CPC分类号： G11C7/1048 , G11C7/08 , G11C7/12 , G11C16/28 , G11C17/12 , G11C2207/005
摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.
摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态的存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。
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公开(公告)号：US20060133128A1
公开(公告)日：2006-06-22
申请号：US11267491
申请日：2005-11-04
CPC分类号： G11C7/1048 , G11C7/08 , G11C7/12 , G11C16/28 , G11C17/12 , G11C2207/005
摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.
摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。
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公开(公告)号：US07457143B2
公开(公告)日：2008-11-25
申请号：US11410432
申请日：2006-04-25
申请人： Gunther Lehmann , Siddharth Gupta , Devesh Dwivedi
发明人： Gunther Lehmann , Siddharth Gupta , Devesh Dwivedi
IPC分类号： G11C17/00
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/14 , G11C7/18 , G11C2207/108
摘要： A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.
摘要翻译： 存储器件具有第一核心存储器阵列，第二核心存储器阵列，第三核心存储器阵列和第四核心存储器阵列，以及用于第一核心存储器阵列和第二核心存储器阵列的第一公共参考部分，以及第二核心存储器阵列 第三核心存储器阵列和第四核心存储器阵列的公共参考部分。 还提供了具有共享信号的另一存储器件和方法。
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公开(公告)号：US20070247954A1
公开(公告)日：2007-10-25
申请号：US11410432
申请日：2006-04-25
申请人： Gunther Lehmann , Siddharth Gupta , Devesh Dwivedi
发明人： Gunther Lehmann , Siddharth Gupta , Devesh Dwivedi
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/14 , G11C7/18 , G11C2207/108
摘要： A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.
摘要翻译： 存储器件具有第一核心存储器阵列，第二核心存储器阵列，第三核心存储器阵列和第四核心存储器阵列，以及用于第一核心存储器阵列和第二核心存储器阵列的第一公共参考部分，以及第二核心存储器阵列 第三核心存储器阵列和第四核心存储器阵列的公共参考部分。 还提供了具有共享信号的另一存储器件和方法。
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公开(公告)号：US20060120124A1
公开(公告)日：2006-06-08
申请号：US11259573
申请日：2005-10-26
IPC分类号： H02M7/04
摘要： A memory arrangement, particularly a ROM, having memory cells, local virtual supply voltage lines, word lines and result lines may also include global virtual supply voltage lines that run along the width of the memory arrangement parallel to the word lines. The local virtual supply voltage lines run parallel to the result lines, and perpendicularly to the word lines where the each local virtual supply voltage line runs only within a block of the memory arrangement. Each global virtual supply voltage line, in each block through which it runs, is connected to one local virtual supply voltage line. The coupling capacitance between the supply voltage lines and the result lines, and the inherent capacitance of the supply voltage lines are reduced, reducing the power consumption and increasing the clock frequency of the memory arrangement.
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公开(公告)号：US07508691B2
公开(公告)日：2009-03-24
申请号：US11259573
申请日：2005-10-26
IPC分类号： G11C5/06
摘要： A memory arrangement, particularly a ROM, having memory cells, local virtual supply voltage lines, word lines and result lines may also include global virtual supply voltage lines that run along the width of the memory arrangement parallel to the word lines. The local virtual supply voltage lines run parallel to the result lines, and perpendicularly to the word lines where the each local virtual supply voltage line runs only within a block of the memory arrangement. Each global virtual supply voltage line, in each block through which it runs, is connected to one local virtual supply voltage line. The coupling capacitance between the supply voltage lines and the result lines, and the inherent capacitance of the supply voltage lines are reduced, reducing the power consumption and increasing the clock frequency of the memory arrangement.
摘要翻译： 具有存储器单元，本地虚拟电源电压线，字线和结果线的存储器布置，特别是ROM，还可以包括沿着与字线平行的存储器布置的宽度延伸的全局虚拟电源电压线。 本地虚拟电源电压线平行于结果线延伸，并垂直于每个本地虚拟电源电压线仅在存储器布置的块内运行的字线。 在其运行的每个块中的每个全局虚拟电源电压线连接到一个本地虚拟电源电压线。 电源电压线和结果线之间的耦合电容以及电源电压线的固有电容减小，降低了功耗并增加了存储器装置的时钟频率。
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公开(公告)号：US20100165754A1
公开(公告)日：2010-07-01
申请号：US12646827
申请日：2009-12-23
CPC分类号： G11C7/22 , G11C7/08 , G11C11/413
摘要： A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.
摘要翻译： 一种用于改善穿过多个电压域的多个信号路径中的信号同步的系统和方法。 根据本公开的实施例，存储器装置优选用于信号同步。 所有读/写和时钟信号和其他控制信号被驱动到周边电源（Vp）电平，除了以核心电源（Vc）电平驱动的字线（WL [i]）信号。 通过这样做，与核心供应（Vc）相关的较低的平均和峰值电流消耗是通过恒定的延迟实现的，并且在穿过多个电压域的信号路径中保持所需的信号同步。
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公开(公告)号：US08526246B2
公开(公告)日：2013-09-03
申请号：US13370035
申请日：2012-02-09
申请人： Siddharth Gupta , Nitin Jain , Anand Mishra
发明人： Siddharth Gupta , Nitin Jain , Anand Mishra
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C7/18 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/413
摘要： A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
摘要翻译： 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。
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