公开(公告)号：US10069586B2

公开(公告)日：2018-09-04

申请号：US13170413

申请日：2011-06-28

申请人： Armin Pitzer ,  Anthony Sanders ,  Christian Jenkner

发明人： Armin Pitzer ,  Anthony Sanders ,  Christian Jenkner

IPC分类号： H04J14/02 ,  H01S3/00 ,  H04J3/16

摘要： The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

公开(公告)号：US20080143386A1

公开(公告)日：2008-06-19

申请号：US11641545

申请日：2006-12-19

申请人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

发明人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509

摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

摘要翻译： 使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。 该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压 可控开关包括电阻元件或与电阻元件分离。 接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。 可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

公开(公告)号：US06975141B2

公开(公告)日：2005-12-13

申请号：US10842985

申请日：2004-05-11

申请人： David Mueller ,  Anthony Sanders

发明人： David Mueller ,  Anthony Sanders

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018514

摘要： The invention relates to an LVDS driver for small supply voltages, particularly of less than 2.0 V, for producing a differential output signal (Pout, Nout), having a pull-up transistor (P3, P4) and a pull-down transistor (P1, P2), respectively, for switching the output voltages which are output at the outputs (Pout, Nout). An optimum switching response and hence an undistorted differential signal can be produced by virtue of the pull-up and pull-down transistors (P1–P4) being in the form of PMOS transistors.

摘要翻译： 本发明涉及用于产生具有上拉晶体管（P 3，P 4）和下拉晶体管（P 3，P 4）的差分输出信号（Pout，Nout）的小电源电压（特别是小于2.0V）的LVDS驱动器 （P 1，P 2），用于切换在输出端（Pout，Nout）输出的输出电压。 可以通过PMOS晶体管形式的上拉和下拉晶体管（P 1 -P 4）来产生最佳的开关响应并因此产生未失真的差分信号。

公开(公告)号：US09001952B2

公开(公告)日：2015-04-07

申请号：US13429815

申请日：2012-03-26

申请人： Anthony Sanders

发明人： Anthony Sanders

IPC分类号： H04L7/00 ,  G06F13/42

CPC分类号： G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

摘要： Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. In one implementation, a method of reducing overall power consumption in a master-slave system includes generating a clock signal in a master device having a first power consumption rate, transmitting the clock signal from the master device to a slave device having a second power consumption rate, the first power consumption rate is lower than the second power consumption rate, sampling data receive by the slave device, the data being provided by the master device, generating phase error information of the clock signal in the slave device, transmitting the phase error information from the slave device to the master device, and adjusting the clock signal in response to the phase error information.

摘要翻译： 描述与使用主从设备的系统，设备和方法相关的实现。 在一个实现中，降低主从系统中的总体功耗的方法包括：在具有第一功率消耗率的主设备中产生时钟信号，将时钟信号从主设备传送到具有第二功耗的从设备 速率，第一功耗率低于第二功率消耗率，由从设备接收的采样数据，数据由主设备提供，产生从设备中的时钟信号的相位误差信息，发送相位误差 从从设备到主设备的信息，以及响应于相位误差信息调整时钟信号。

公开(公告)号：US08699647B2

公开(公告)日：2014-04-15

申请号：US12490185

申请日：2009-06-23

申请人： Holger Wenske ,  Anthony Sanders ,  Christian Kreuzer

发明人： Holger Wenske ,  Anthony Sanders ,  Christian Kreuzer

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091

摘要： Disclosed herein are systems and methods for fast phase alignment and clock and data recovery. Systems and methods may include a fast phase alignment component configured to generate a selected phase signal based on a characteristic of an incoming signal. A clock and data recovery component may also be configured to receive the selected phase signal and perform a clock and data recovery function on the incoming signal using the selected phase signal.

摘要翻译： 这里公开了用于快速相位对准和时钟和数据恢复的系统和方法。 系统和方法可以包括快速相位对准部件，其被配置为基于输入信号的特性产生所选择的相位信号。 时钟和数据恢复组件还可以被配置为接收所选择的相位信号，并且使用所选择的相位信号对输入信号执行时钟和数据恢复功能。

公开(公告)号：US08204167B2

公开(公告)日：2012-06-19

申请号：US12124476

申请日：2008-05-21

申请人： Anthony Sanders

发明人： Anthony Sanders

IPC分类号： H04L7/00 ,  G06F15/16

CPC分类号： G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

摘要： Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. In some implementations, a master device is configured to generate a clock signal and a slave device is coupled to the master device and is configured to receive the clock signal. The clock signal may control data behavior associated with the master device and the slave device. Additionally, the master device may have a power consumption rate that is lower than the power consumption rate of the slave device.

摘要翻译： 描述与使用主从设备的系统，设备和方法相关的实现。 在一些实现中，主设备被配置为生成时钟信号，并且从设备耦合到主设备并且被配置为接收时钟信号。 时钟信号可以控制与主设备和从设备相关联的数据行为。 此外，主设备可以具有低于从设备的功耗率的功率消耗率。

公开(公告)号：US20090013114A1

公开(公告)日：2009-01-08

申请号：US12124476

申请日：2008-05-21

申请人： Anthony Sanders

发明人： Anthony Sanders

IPC分类号： G06F13/40

CPC分类号： G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

摘要： Implementations related to systems, devices, and methods that make use of a master slave arrangement are described.

摘要翻译： 描述与使用主从设备的系统，设备和方法相关的实现。

公开(公告)号：US07420430B2

公开(公告)日：2008-09-02

申请号：US11194494

申请日：2005-08-01

申请人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

发明人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

IPC分类号： H03B28/00

CPC分类号： H03K5/13 ,  H03K2005/00286 ,  H04L7/0025

摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

摘要翻译： 用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。 提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。 累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。 具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

公开(公告)号：US20070183553A1

公开(公告)日：2007-08-09

申请号：US11346905

申请日：2006-02-03

申请人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

发明人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/093

摘要： A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

摘要翻译： 时钟和数据恢复电路包括相位检测器，被配置为将数据信号的相位与采样时钟的相位进行比较以提供相位误差信号;增益级，被配置为对相位误差信号施加增益以提供放大 相位误差信号，以及被配置为对放大的相位误差信号进行滤波以提供相位校正信号的滤波器。 该电路包括：增益控制器，被配置为响应于相位校正信号调整增益级的增益;以及时钟发生器，被配置为基于相位校正信号提供采样时钟。

公开(公告)号：US20070177702A1

公开(公告)日：2007-08-02

申请号：US11338176

申请日：2006-01-23

申请人： Anthony Sanders ,  Matthias Schobinger ,  Edoardo Prete ,  Norbert Neurohr ,  Johannes Sturm ,  Eva Tatschl-Unterberger ,  Nicola Dadalt ,  Daniele Gardellini

发明人： Anthony Sanders ,  Matthias Schobinger ,  Edoardo Prete ,  Norbert Neurohr ,  Johannes Sturm ,  Eva Tatschl-Unterberger ,  Nicola Dadalt ,  Daniele Gardellini

IPC分类号： H03D3/24

CPC分类号： H04L7/0058

摘要： A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.

摘要翻译： 一种接收数据的方法包括对数据采样点的数据进行采样，以获取与数据中包含的信息相对应的数据采样，并在数据采样点之间的中间采样点采样数据，以获得中间样本。 取决于在至少一个中间采样点之前的数据采样点采样的先前数据采样点和在数据采样中采样的先前中间采样点之间的至少一个数据样本，在中间采样点的至少一个中间采样点处对数据进行校正 在所述至少一个中间采样点之前。