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公开(公告)号：US20120155632A1
公开(公告)日：2012-06-21
申请号：US13406567
申请日：2012-02-28
IPC分类号： H04M1/00
CPC分类号： H04M9/00 , A61F7/12 , A61F2007/126
摘要： A CODEC circuit for POTS system comprises a digital circuit for outputting a digital control signal having a first bit width, the digital control signal being indicative of a voltage to be applied to a POTS subscriber line pair. Further, the CODEC comprises a noise shaper coupled to an output of the digital circuit for generating a noise-shaped control signal and a digital-to-analog converter coupled to an output of the noise shaper, the input of the digital-to-analog converter having a second bit width being larger than 1 and smaller than the first bit width.
摘要翻译： 用于POTS系统的CODEC电路包括用于输出具有第一位宽度的数字控制信号的数字电路，数字控制信号指示要施加到POTS用户线对的电压。 此外，CODEC包括耦合到数字电路的输出的噪声整形器，用于产生噪声形状的控制信号，以及耦合到噪声整形器的输出的数模转换器，数模转换器 转换器具有大于1且小于第一位宽度的第二位宽度。
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公开(公告)号：US20120051751A1
公开(公告)日：2012-03-01
申请号：US13170413
申请日：2011-06-28
申请人： Armin PITZER , Anthony SANDERS , Christian JENKNER
发明人： Armin PITZER , Anthony SANDERS , Christian JENKNER
IPC分类号： H04J14/08
CPC分类号： H04J3/1694
摘要： The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.
摘要翻译： 所描述的实现涉及无源光网络（PON）。 在一个实现中，PON包括具有至少一个发射机子系统组件和相关联的光发射机的光网络单元（ONU）。 至少一个发射机子系统组件可以被配置为在分配给ONU的时隙周期内处于使能状态，用于在时隙结束之后发送上行数据突发和禁用状态。
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公开(公告)号：US08111824B2
公开(公告)日：2012-02-07
申请号：US12057547
申请日：2008-03-28
CPC分类号： H04M19/005
摘要： A control device for controlling a supply voltage which can be switched between a constant line current operation and a constant line voltage operation, wherein a line current, which consists of a direct current for supplying the terminal and of an alternating current for transmitting information, flows via a subscriber line of a terminal, comprising a sensing circuit for sensing an analogue input voltage dependent on the line current, a subtractor which, in the constant line current operation, subtracts an analogue feedback voltage dependent on an adjustable nominal direct-current value from the sensed input voltage for generating an analogue difference voltage, an analogue/digital converter for converting the generated analogue difference voltage into a digital difference voltage value, a digital low-pass filter for filtering a sequence of control error values out of the generated sequence of difference voltage values, a controller for generating a control value in dependence on the filtered-out sequence of control error values, and comprising a first digital/analogue converter which, in the constant line current operation, converts the control value in each case generated by the controller into the analogue direct voltage for supplying the terminal.
摘要翻译： 一种用于控制能够在恒定电流电流操作和恒定电压操作之间切换的电源电压的控制装置，其中由用于提供所述端子的直流电流和用于传输信息的交流电流组成的线路电流流动 通过终端的用户线路，包括用于感测取决于线路电流的模拟输入电压的感测电路;减法器，其在恒定电流电流操作中，根据可调整的标称直流电流值减去模拟反馈电压， 感测的用于产生模拟差分电压的输入电压，用于将所产生的模拟差分电压转换为数字差分电压值的模/数转换器，数字低通滤波器，用于从所生成的序列中产生的序列 差分电压值，用于根据所述控制值产生控制值的控制器 滤波出的控制误差值序列，并且包括第一数字/模拟转换器，其在恒定电流电流操作中将由控制器产生的每种情况下的控制值转换成用于提供端子的模拟直流电压。
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公开(公告)号：US07496150B2
公开(公告)日：2009-02-24
申请号：US10977711
申请日：2004-10-29
IPC分类号： H04M7/04
CPC分类号： H04B14/04 , H04L25/0278 , H04L25/028
摘要： The invention provides a transmission apparatus (100) for transmission of electrical signals between a line driver (205), which is connected to a transmission line (201), and a switching center (301), having an analog feedback device (101) for coarse setting of a line voltage level (210) on the transmission line (201), and a digital feedback device (102), which is coupled to the analog feedback device (101) and has a feedback filter device (118), designed such that a filter input signal (404) can be converted to a filter output signal (405) at a rate which is lower than the sampling rate (fa) of an analog/digital converter (104).
摘要翻译： 本发明提供了一种用于在连接到传输线（201）的线路驱动器（205）和交换中心（301）之间传输电信号的发送设备（100），该交换中心具有模拟反馈设备（101） 在传输线（201）上的线路电压电平（210）的粗略设置以及耦合到模拟反馈装置（101）并具有反馈滤波器装置（118）的数字反馈装置（102） 滤波器输入信号（404）可以以比模拟/数字转换器（104）的采样率（fa）低的速率被转换成滤波器输出信号（405）。
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公开(公告)号：US20080170682A1
公开(公告)日：2008-07-17
申请号：US11623283
申请日：2007-01-15
IPC分类号： H04M9/00
CPC分类号： H04M9/00 , A61F7/12 , A61F2007/126
摘要： A CODEC circuit for POTS system comprises a digital circuit for outputting a digital control signal having a first bit width, the digital control signal being indicative of a voltage to be applied to a POTS subscriber line pair. Further, the CODEC circuit comprises a noise shaper coupled to an output of the digital circuit for generating a noise-shaped control signal and a digital-to-analog converter coupled to an output of the noise shaper, the input of the digital-to-analog converter having a second bit width being larger than 1 and smaller than the first bit width.
摘要翻译： 用于POTS系统的CODEC电路包括用于输出具有第一位宽度的数字控制信号的数字电路，数字控制信号指示要施加到POTS用户线对的电压。 此外，CODEC电路包括耦合到数字电路的输出的噪声整形器，用于产生噪声形状的控制信号，以及耦合到噪声整形器的输出的数模转换器，数字 - 模拟转换器具有大于1且小于第一位宽的第二位宽度。
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6.发明授权Method and arrangement for determining phase changes of a reference input signal of a phase-locked loop 失效用于确定锁相环参考输入信号的相位变化的方法和装置
公开(公告)号：US5596300A
公开(公告)日：1997-01-21
申请号：US553066
申请日：1995-11-03
申请人： Werner Dietrich , Christian Jenkner
发明人： Werner Dietrich , Christian Jenkner
摘要： A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).
摘要翻译： 处理器（PR）在锁相环中连接到相位比较器（PK）的输出端。 处理器（PR）在相位比较器（PK）的输出处的相位差（DELTA phi）中计算观测时间间隔内的输入信号（fE）的相移（例如，DELTA t = 0-T） 以及锁相环（FT1，PK，FI，VCO，FT2）的参数。
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公开(公告)号：US10069586B2
公开(公告)日：2018-09-04
申请号：US13170413
申请日：2011-06-28
申请人： Armin Pitzer , Anthony Sanders , Christian Jenkner
发明人： Armin Pitzer , Anthony Sanders , Christian Jenkner
摘要： The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.
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公开(公告)号：US08787559B2
公开(公告)日：2014-07-22
申请号：US13406567
申请日：2012-02-28
CPC分类号： H04M9/00 , A61F7/12 , A61F2007/126
摘要： A CODEC circuit for POTS system comprises a digital circuit for outputting a digital control signal having a first bit width, the digital control signal being indicative of a voltage to be applied to a POTS subscriber line pair. Further, the CODEC comprises a noise shaper coupled to an output of the digital circuit for generating a noise-shaped control signal and a digital-to-analog converter coupled to an output of the noise shaper, the input of the digital-to-analog converter having a second bit width being larger than 1 and smaller than the first bit width.
摘要翻译： 用于POTS系统的CODEC电路包括用于输出具有第一位宽度的数字控制信号的数字电路，数字控制信号指示要施加到POTS用户线对的电压。 此外，CODEC包括耦合到数字电路的输出的噪声整形器，用于产生噪声形状的控制信号，以及耦合到噪声整形器的输出的数模转换器，数模转换器 转换器具有大于1且小于第一位宽度的第二位宽度。
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公开(公告)号：US08243916B2
公开(公告)日：2012-08-14
申请号：US11623283
申请日：2007-01-15
IPC分类号： H04M1/00
CPC分类号： H04M9/00 , A61F7/12 , A61F2007/126
摘要： A CODEC circuit for POTS system comprises a digital circuit for outputting a digital control signal having a first bit width, the digital control signal being indicative of a voltage to be applied to a POTS subscriber line pair. Further, the CODEC circuit comprises a noise shaper coupled to an output of the digital circuit for generating a noise-shaped control signal and a digital-to-analog converter coupled to an output of the noise shaper, the input of the digital-to-analog converter having a second bit width being larger than 1 and smaller than the first bit width.
摘要翻译： 用于POTS系统的CODEC电路包括用于输出具有第一位宽度的数字控制信号的数字电路，数字控制信号指示要施加到POTS用户线对的电压。 此外，CODEC电路包括耦合到数字电路的输出的噪声整形器，用于产生噪声形状的控制信号，以及耦合到噪声整形器的输出的数模转换器，数字 - 模拟转换器具有大于1且小于第一位宽的第二位宽度。
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10.发明授权Method for transmitting digital data over a capacitive interface with data integrity 有权通过数据完整性通过电容接口发送数字数据的方法公开(公告)号：US06430245B1
公开(公告)日：2002-08-06
申请号：US09240717
申请日：1999-01-29
申请人： Christian Jenkner , Michael Staber
发明人： Christian Jenkner , Michael Staber
IPC分类号： H04L2300
CPC分类号： H04L7/04 , H04L7/041 , H04L25/0266
摘要： A method of using a capacitively coupled interface to increase the integrity of digital signals being transmitted across the interface includes transmitting signals between a first electronic circuit and a second electronic circuit using a capacitively coupled interface, and protecting the integrity of the signals by using a protocol. The protocol preferably includes: Transmitting a signal from the first electronic circuit to the second electronic circuit on the capacitively coupled interface. After the second electronic circuit receives the signal from the first electronic circuit, transmitting a unique synchronization sequence from the second electronic circuit to the first electronic circuit on the capacitively coupled interface. Constructing a status signal that contains information concerning a status of the first electronic circuit. After the first electronic circuit receives the unique synchronization sequence, transmitting the status signal and a data signal from the first electronic circuit for reception by the second electronic circuit on the capacitively coupled interface. Determining if the received status signal corresponds to a predetermined status signal, and if the received status signal corresponds to the predetermined status signal, determining that the received data signal is valid.
摘要翻译： 使用电容耦合接口来提高跨接口传输的数字信号的完整性的方法包括使用电容耦合接口在第一电子电路和第二电子电路之间传输信号，并且通过使用协议来保护信号的完整性 。 该协议优选地包括：在电容耦合接口上将信号从第一电子电路传输到第二电子电路。 在第二电子电路接收到来自第一电子电路的信号之后，在电容耦合接口上从第二电子电路向第一电子电路发送唯一同步序列。 构造包含有关第一电子电路状态信息的状态信号。 在第一电子电路接收到唯一同步序列之后，从第一电子电路发送状态信号和数据信号，以便由电容耦合接口上的第二电子电路接收。 确定接收到的状态信号是否对应于预定状态信号，并且如果接收到的状态信号对应于预定状态信号，则确定所接收的数据信号是有效的。
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