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    Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks
    1.
    发明授权
    Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks 有权
    使用具有合并的功能和测试逻辑块的硬件描述制造半导体器件的方法和装置

    公开(公告)号：US07844937B2

    公开(公告)日：2010-11-30

    申请号：US11951558

    申请日：2007-12-06

    申请人： Arvind Raman ,  Ravi Gupta

    发明人： Arvind Raman ,  Ravi Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/14

    摘要： A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.

    摘要翻译： 提供了一种用于制造具有测试逻辑块和功能逻辑块的半导体器件的处理器实现的方法。 该方法包括检索至少一个测试逻辑块的硬件描述，并将至少一个测试逻辑块的硬件描述映射到逻辑门以生成至少一个合成测试逻辑块。 该方法还包括检索至少一个功能逻辑块的硬件描述，并将至少一个功能逻辑块的硬件描述映射到逻辑门以生成至少一个合成功能逻辑块。 该方法还包括当至少一个功能逻辑块满足至少一个用于选择的标准作为用于与至少一个测试逻辑块合并的候选者时，将至少一个合成测试逻辑块与至少一个合成功能逻辑块合并 。

    METHOD AND APPARATUS FOR MAKING A SEMICONDUCTOR DEVICE USING HARDWARE DESCRIPTION HAVING MERGED FUNCTIONAL AND TEST LOGIC BLOCKS
    2.
    发明申请
    METHOD AND APPARATUS FOR MAKING A SEMICONDUCTOR DEVICE USING HARDWARE DESCRIPTION HAVING MERGED FUNCTIONAL AND TEST LOGIC BLOCKS 有权
    使用具有合并功能和测试逻辑块的硬件描述制造半导体器件的方法和装置

    公开(公告)号：US20090150843A1

    公开(公告)日：2009-06-11

    申请号：US11951558

    申请日：2007-12-06

    申请人： Arvind Raman ,  Ravi Gupta

    发明人： Arvind Raman ,  Ravi Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/14

    摘要： A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.

    摘要翻译： 提供了一种用于制造具有测试逻辑块和功能逻辑块的半导体器件的处理器实现的方法。 该方法包括检索至少一个测试逻辑块的硬件描述，并将至少一个测试逻辑块的硬件描述映射到逻辑门以生成至少一个合成测试逻辑块。 该方法还包括检索至少一个功能逻辑块的硬件描述，并将至少一个功能逻辑块的硬件描述映射到逻辑门以生成至少一个合成功能逻辑块。 该方法还包括当至少一个功能逻辑块满足至少一个用于选择的标准作为用于与至少一个测试逻辑块合并的候选者时，将至少一个合成测试逻辑块与至少一个合成功能逻辑块合并 。

    Receiving policy data from a server to address theft and unauthorized access of a client
    3.
    发明授权
    Receiving policy data from a server to address theft and unauthorized access of a client 有权
    从服务器接收策略数据，以解决客户端的窃取和未经授权的访问

    公开(公告)号：US08332953B2

    公开(公告)日：2012-12-11

    申请号：US12538040

    申请日：2009-08-07

    申请人： Jacques Lemieux ,  Anahit Tarkhanyan ,  Ravi Gupta ,  Gaurav Banga

    发明人： Jacques Lemieux ,  Anahit Tarkhanyan ,  Ravi Gupta ,  Gaurav Banga

    IPC分类号： G06F7/04

    CPC分类号： G06F21/57 ,  G06F21/88

    摘要： Techniques for securing a client. When a client, such as a portable computer, undergoes a change in operational state, an operating system agent sends a state message to a server. The state message describes the change in the operational state of the client. The operating system agent is one or more software modules that execute in an operating system of the client. The client receives a policy message from the server. The policy message contains policy data, which a BIOS agent stores in the BIOS of the client. The policy data identifies one or more security policies which the client should follow.

    摘要翻译： 确保客户端的技术。 当诸如便携式计算机的客户端经历操作状态的改变时，操作系统代理向服务器发送状态消息。 状态消息描述客户端操作状态的变化。 操作系统代理是在客户机的操作系统中执行的一个或多个软件模块。 客户端从服务器收到策略消息。 策略消息包含一个BIOS代理存储在客户端的BIOS中的策略数据。 策略数据标识客户端应遵循的一个或多个安全策略。

    Method and system for generating sample plate layout for validation
    4.
    发明申请
    Method and system for generating sample plate layout for validation 审中-公开
    用于生成样本板布局以进行验证的方法和系统

    公开(公告)号：US20070207490A1

    公开(公告)日：2007-09-06

    申请号：US11714408

    申请日：2007-03-06

    申请人： Jacquelyn Benfield ,  Ravi Gupta ,  Ralph Jocham ,  Pui-Ling Lam

    发明人： Jacquelyn Benfield ,  Ravi Gupta ,  Ralph Jocham ,  Pui-Ling Lam

    IPC分类号： C12Q1/68 ,  G06F19/00 ,  C12M3/00

    CPC分类号： G06Q10/06 ,  B01J2219/00695 ,  G01N35/00594 ,  G01N35/0092 ,  G01N2035/00653 ,  G01N2035/0094 ,  G06Q10/00 ,  G16B50/00 ,  G16H10/40

    摘要： Systems and methods are provided that relate to a platform, techniques, and processes for verifying the precision, sensitivity, accuracy, reproducibility, and other characteristics of biological tests, such as DNA identification or other tests or assays. According to various embodiments, a logic engine can guide a user to arrange, conduct, and record studies designed to ensure that chemistry kits and laboratory operations return dependably valid results. The validation platform can manage the design of the entire validation workflow, from initiation of a verification project for one or more chemistry kits or other assays or equipment, to design of individual studies to test the accuracy, sensitivity, reproducibility, and other parameters of biological testing. The validation engine can automatically generate a sample plate layout to conduct individual assays. The validation engine can likewise automatically generate unified data output recording the studies which were undertaken, the assays used, tests results, and other data.

    摘要翻译： 提供了与用于验证生物测试的精度，灵敏度，准确性，可重复性和其他特征（如DNA鉴定或其他测试或测定）的平台，技术和过程相关的系统和方法。 根据各种实施例，逻辑引擎可以引导用户安排，进行和记录旨在确保化学试剂盒和实验室操作返回可靠的有效结果的研究。 验证平台可以管理整个验证工作流程的设计，从启动一个或多个化学试剂盒或其他测定或设备的验证项目到设计个体研究以测试生物学的准确性，灵敏度，可重复性和其他参数 测试。 验证引擎可以自动生成样本板布局以进行单独的测定。 验证引擎同样可以自动生成统一的数据输出，记录所进行的研究，所用测定，测试结果和其他数据。

    Secure computing environment to address theft and unauthorized access
    7.
    发明授权
    Secure computing environment to address theft and unauthorized access 有权
    安全的计算环境来解决盗用和未经授权的访问

    公开(公告)号：US08510825B2

    公开(公告)日：2013-08-13

    申请号：US12538033

    申请日：2009-08-07

    申请人： Anahit Tarkhanyan ,  Ravi Gupta ,  Gaurav Banga

    发明人： Anahit Tarkhanyan ,  Ravi Gupta ,  Gaurav Banga

    IPC分类号： G06F7/04

    CPC分类号： G06F21/57 ,  G06F21/88

    摘要： Techniques for securing a client. A BIOS agent stores policy data within a BIOS of the client. The BIOS agent is one or more software modules that execute in the BIOS of the client. The policy data describes one or more policies which the client should follow. When an operating system agent detects that a condition, specified by a particular policy of the one or more policies, has been met, the operating system agent performs one or more actions specified by the particular policy, such as disabling the client, retrieving a file from the client, erasing a file from the client, or encrypting a file on the client. The operating system agent is one or more software modules that execute in the operating system of the client.

    摘要翻译： 确保客户端的技术。 BIOS代理将策略数据存储在客户机的BIOS中。 BIOS代理是在客户端的BIOS中执行的一个或多个软件模块。 策略数据描述客户端应遵循的一个或多个策略。 当操作系统代理检测到由一个或多个策略的特定策略指定的条件已经被满足时，操作系统代理执行特定策略指定的一个或多个动作，诸如禁用客户端，检索文件 从客户端删除客户端的文件，或加密客户端上的文件。 操作系统代理是在客户端的操作系统中执行的一个或多个软件模块。

    Secure platform management with power savings capacity
    8.
    发明授权
    Secure platform management with power savings capacity 有权
    安全平台管理，节省能力

    公开(公告)号：US08346234B2

    公开(公告)日：2013-01-01

    申请号：US12321504

    申请日：2009-01-21

    申请人： Gaurav Banga ,  Ravi Gupta ,  Anahit Tarkhanyan

    发明人： Gaurav Banga ,  Ravi Gupta ,  Anahit Tarkhanyan

    IPC分类号： H04M3/00

    CPC分类号： H04M1/7253 ,  G06F1/3203 ,  G06F1/3231 ,  G06F21/35 ,  G06F21/81 ,  H04M2250/02 ,  H04W52/0245 ,  Y02D10/173 ,  Y02D70/144 ,  Y02D70/166

    摘要： An electronic device, for example, a laptop computer includes a processor, a transceiver module, for example, a Bluetooth module and a memory. The memory includes a platform proximity agent, which may be implemented as a series of instructions, which when executed by the processor, causes the processor to receive a Bluetooth signal from a corresponding provisioned Bluetooth device, for example, a cellular telephone. Next, determine whether the received signal exceeds both a strength threshold level and a predetermined time threshold level, where the signal strength and time threshold levels are established when the laptop and a corresponding cell phone are paired during a provisioning process. When the received signal strength and duration both exceed the corresponding policy based thresholds, the laptop enters (or remains in) a full power state with full access to the monitor and the platform. On the other hand, when the received signal strength and duration both fall below (or are less than) the corresponding policy based threshold, the laptop enters (or remains in) a reduced power, or locked state.

    摘要翻译： 电子设备，例如膝上型计算机，包括处理器，收发器模块，例如蓝牙模块和存储器。 存储器包括平台邻近代理，其可以被实现为一系列指令，当由处理器执行时，处理器从相应的所提供的蓝牙设备（例如，蜂窝电话）接收蓝牙信号。 接下来，确定接收到的信号是否超过强度阈值电平和预定时间阈值电平，其中当在供应处理期间膝上型电脑和相应的蜂窝电话配对时，建立信号强度和时间阈值电平。 当接收到的信号强度和持续时间都超过相应的基于策略的阈值时，笔记本电脑进入（或保持）全功率状态，完全访问监视器和平台。 另一方面，当接收到的信号强度和持续时间都低于（或小于）相应的基于策略的阈值时，笔记本电脑进入（或保持）降低功率或锁定状态。