公开(公告)号：US5638524A

公开(公告)日：1997-06-10

申请号：US443199

申请日：1995-05-17

申请人： Atsushi Kiuchi ,  Toru Baji ,  Tetsuya Nakagawa ,  Kenji Kaneko

发明人： Atsushi Kiuchi ,  Toru Baji ,  Tetsuya Nakagawa ,  Kenji Kaneko

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3822

摘要： A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations. One of the source and destination fields in the predefined RISC instruction word has more bits than the corresponding field in the predefined DSP instruction word. The instruction decoder decodes the selected instruction.

摘要翻译： 一种包括指令存储器，程序控制单元和指令译码器的数字信号处理器。 指令存储器存储包括DSP指令字和RISC指令字的指令字序列。 程序控制单元向指令存储器输出指令地址，以便在指令存储器中选择一个指令字。 每个DSP指令字标识要执行的一个数据处理操作和一个数据传送操作。 DSP指令字包括具有用于指定数据源和数据目的地的寄存器位置的独立源和目的地字段的预定义DSP指令字。 RISC指令字包括与预定义的DSP指令字对应的预定RISC指令字。 预定义的RISC指令字具有用于指定数据源和数据目的地的寄存器位置的单独的源和目标字段。 预定义RISC指令字中的源和目标字段之一具有比预定义DSP指令字中相应字段更多的位。 指令译码器解码所选择的指令。

公开(公告)号：US4809206A

公开(公告)日：1989-02-28

申请号：US87346

申请日：1987-08-20

申请人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

发明人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

IPC分类号： G06F9/34 ,  G06F7/544 ,  G06F12/02 ,  G06F17/10 ,  H03H17/02 ,  G06F7/38

CPC分类号： G06F7/5443

摘要： This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.

摘要翻译： 本发明涉及诸如数字信号处理器的信息处理设备，并且特别适用于数字滤波器。 从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中，并且通过地址运算单元的增量操作被依次读出。 数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算，进行数字信号处理。 该信息处理装置特别地具有如下装置：当访问地址从初始值开始时，由于增量操作而超过最终值并达到返回地址，自动将访问地址返回到初始值。 因此，可以重复使用存储在数据存储器中的多个数据。 为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值，进行了操作。

公开(公告)号：US4958276A

公开(公告)日：1990-09-18

申请号：US128585

申请日：1987-12-04

申请人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Takashi Akazawa ,  Tomoru Sato

发明人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Takashi Akazawa ,  Tomoru Sato

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/06 ,  G06F15/78

CPC分类号： G06F9/3814 ,  G06F15/7842 ,  G06F9/3802

摘要： In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

摘要翻译： 在可以设置有扩展程序存储器的单芯片处理器中，通过改变有效指令周期，可以执行高速访问，而不受外部程序存储器的访问时间的限制，通过使用内部程序存储器， 因此能够获得存储节目类型的单芯片处理器的高速处理性能。

公开(公告)号：US4910466A

公开(公告)日：1990-03-20

申请号：US304878

申请日：1989-01-31

申请人： Atsushi Kiuchi ,  Jun Ishida ,  Kenji Kaneko ,  Tetsuya Nakagawa ,  Tomoru Sato ,  Shigeki Masumura ,  Noriyasu Suzuki ,  Yoshimune Hagiwara

发明人： Atsushi Kiuchi ,  Jun Ishida ,  Kenji Kaneko ,  Tetsuya Nakagawa ,  Tomoru Sato ,  Shigeki Masumura ,  Noriyasu Suzuki ,  Yoshimune Hagiwara

IPC分类号： H03K17/00 ,  H03K17/693

CPC分类号： H03K17/693

摘要： A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.

摘要翻译： 多个外部输入信息被添加到选择电路。 选择电路的输出作为外部输入信息之一反馈给选择电路。 输入信号组被解码，并作为控制信号产生，以便与时钟信号同步地指定外部输入信息。 当输入选择信号组具有非选择模式时，必须选择反馈的输出。

公开(公告)号：US4745581A

公开(公告)日：1988-05-17

申请号：US855928

申请日：1986-04-25

申请人： Tomoru Sato ,  Kenji Kaneko ,  Hirotada Ueda ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Tetsuya Nakagawa ,  Atsushi Kiuchi

发明人： Tomoru Sato ,  Kenji Kaneko ,  Hirotada Ueda ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Tetsuya Nakagawa ,  Atsushi Kiuchi

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/36 ,  G11C13/00 ,  G11C11/40

CPC分类号： G06F11/3648 ,  G06F11/0721 ,  G06F11/0772

摘要： An LSI system is disclosed in which a plurality of status registers for indicating the internal status of the system are connected to each other so as to form a hierarchical structure and the contents of each of the remaining status registers other than one status register can be transferred to an output register through a bus, to make it possible to provide additional status registers in the system without increasing the number of address signals used and the number of pins connected to external address signal lines.

摘要翻译： 公开了一种LSI系统，其中用于指示系统的内部状态的多个状态寄存器彼此连接以形成分层结构，并且可以传送除了一个状态寄存器之外的每个剩余状态寄存器的内容 通过总线连接到输出寄存器，以便在不增加使用的地址信号数量和连接到外部地址信号线的引脚数的情况下，在系统中提供附加的状态寄存器。

公开(公告)号：US5430885A

公开(公告)日：1995-07-04

申请号：US782760

申请日：1991-10-22

申请人： Kenji Kaneko ,  Hirotada Ueda ,  Tetsuya Nakagawa ,  Atsuchi Kiuchi ,  Yoshimune Hagiwara ,  You Takamori ,  Takanori Toyomasu

发明人： Kenji Kaneko ,  Hirotada Ueda ,  Tetsuya Nakagawa ,  Atsuchi Kiuchi ,  Yoshimune Hagiwara ,  You Takamori ,  Takanori Toyomasu

IPC分类号： G06F15/16 ,  G06F9/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06T1/20

CPC分类号： G06F15/8007 ,  G06F15/17337 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06T1/20

摘要： A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.

摘要翻译： 用于多维图像信号处理的多处理器系统包括多个协处理器和通过总线向处理器发出处理器号码和命令的主机处理器。 由于处理器号码的多维特性，图像信号的给定范围的数据处理可由协处理器共享。 由主计算机发行的特定多维处理器号码，允许在主机处理器和协处理器之间执行同时通信。

公开(公告)号：US4752905A

公开(公告)日：1988-06-21

申请号：US795451

申请日：1985-11-06

申请人： Tetsuya Nakagawa ,  Kenji Kaneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

发明人： Tetsuya Nakagawa ,  Kenji Kaneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5318 ,  G06F7/5338

摘要： A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.

摘要翻译： 适用于VLSI的高速倍增器，其具有规则排列的结构，其数量减少。 提供了进位保存加法器电路，其中对输入到全加器的信号赋予时间差，以便消除信号传播中的额外等待时间。 也就是说，输入两级的全加器的进位信号，速度增加为1 / 2TFA。

公开(公告)号：US20090165920A1

公开(公告)日：2009-07-02

申请号：US12403460

申请日：2009-03-13

申请人： Tomoo Yamaguchi ,  Masayuki Ishikawa ,  Kenji Kaneko ,  Kazumasa Asano ,  Yasunobu Ina

发明人： Tomoo Yamaguchi ,  Masayuki Ishikawa ,  Kenji Kaneko ,  Kazumasa Asano ,  Yasunobu Ina

IPC分类号： B32B37/00

CPC分类号： C09J7/22 ,  C09J7/38 ,  C09J7/383 ,  C09J2201/128 ,  C09J2421/00 ,  Y10T428/2848 ,  Y10T428/2857

摘要： A pressure-sensitive adhesive double-coated sheet comprising a substrate, a pressure-sensitive adhesive layer (A) formed on one side of the substrate and a pressure-sensitive adhesive layer (B) formed on the other side of the substrate, wherein at least the pressure-sensitive adhesive layer (A) is formed with a pressure-sensitive adhesive comprising a butyl rubber as base material, and after the pressure-sensitive adhesive double-coated sheet is allowed to stand at 60° C. for five days while being placed between a moisture vapor-permeable waterproof sheet attached to the adhesive layer (A) and an aluminum plate attached to the adhesive layer (B), an expansion coefficient of the moisture vapor-permeable waterproof sheet is 0.5% or less. The pressure-sensitive adhesive double-coated sheet can allow the moisture vapor-permeable waterproof sheet to less expand over time when attached between the moisture vapor-permeable waterproof sheet and the adherend in a waterproof airtight structure of a construction.

摘要翻译： 一种压敏粘合剂双面涂布片，其包含基材，形成在所述基材一侧上的粘合剂层（A）和形成在所述基材的另一侧上的压敏粘合剂层（B），其中在 至少压敏粘合剂层（A）由包含丁基橡胶作为基材的压敏粘合剂形成，并且将压敏粘合剂双面涂布片在60℃下放置5天， 放置在附着在粘合剂层（A）的透湿性防水薄片和附着在粘合剂层（B）上的铝板之间，透湿防水薄膜的膨胀系数为0.5％以下。 粘合剂双面涂布片可以在构造的防水密封结构中，在透湿水性防水片和被粘物之间附着时，能够使透湿性防水薄片随时间扩张。

公开(公告)号：US07509891B2

公开(公告)日：2009-03-31

申请号：US10545301

申请日：2004-02-13

申请人： Suyako Miyake ,  Kenji Kaneko ,  Kaori Ojima ,  Yukie Momoi ,  Keiichi Kazami ,  Kenetsu Kikuchi ,  Mitsuo Tamura ,  Iwakichi Ogawa

发明人： Suyako Miyake ,  Kenji Kaneko ,  Kaori Ojima ,  Yukie Momoi ,  Keiichi Kazami ,  Kenetsu Kikuchi ,  Mitsuo Tamura ,  Iwakichi Ogawa

IPC分类号： A44B1/00

CPC分类号： A44B1/126 ,  A44C3/001 ,  A44C27/00 ,  Y10T24/36

摘要： A button making device capable of simply exchanging a first pressed mold, a second pressed mold, and a pressing mold so as to produce buttons of different sizes; a polygonal button whose front surface plate is dome-wise curved and has its shape fixed; and such a button making device, are provided. The button making device has a sliding platform, two pressed molds, a fixed member, a pressing shaft, a pressing mold, and an operation mechanism. The pressed molds are provided on an attachment member which is removably attached to the sliding platform. The pressing mold is removably attached to a lower end of the pressing shaft using magnetic force. The present invention can be used for a button making device which can easily form a metal button by press processing which can be used as an accessory adhered to clothes or the like by a pin or the like.

摘要翻译： 一种按钮制造装置，其能够简单地更换第一压制模具，第二压制模具和按压模具，以便产生不同尺寸的按钮; 一个多边形按钮，其前表面板圆顶弯曲并具有固定的形状; 和这样的按钮制造装置。 按钮制造装置具有滑动平台，两个压模，固定构件，按压轴，压模和操作机构。 压模设置在可移除地附接到滑动平台的附接构件上。 按压模具利用磁力可拆卸地安装在按压轴的下端。 本发明可以用于能够通过冲压加工容易地形成金属按钮的按钮制造装置，该按压制造装置可以用作通过销等附着在衣服等上的附件。

公开(公告)号：US20080110227A1

公开(公告)日：2008-05-15

申请号：US12002967

申请日：2007-12-19

申请人： Zenji Horita ,  Katsuaki Nakamura ,  Koji Neishi ,  Michihiko Nakagaki ,  Kenji Kaneko

发明人： Zenji Horita ,  Katsuaki Nakamura ,  Koji Neishi ,  Michihiko Nakagaki ,  Kenji Kaneko

IPC分类号： B21D31/00

CPC分类号： C21D7/02 ,  B21C23/001 ,  B21J1/025 ,  B62D27/023 ,  C21D7/00 ,  C21D7/13 ,  C21D9/0075 ,  C21D9/08 ,  C21D9/28 ,  C21D9/60 ,  C21D10/00 ,  C21D2201/03 ,  C21D2221/00 ,  C21D2251/00 ,  C21D2281/00 ,  C22F1/00 ,  Y02P10/253 ,  Y10S72/71 ,  Y10T428/12

摘要： A method of working metal in which the microstructure of metal body is rendered fine to thereby enhance the strength, ductility or homogeneity thereof; a metal body obtained by the metal working method; and a metal-containing ceramic body obtained by the metal working method. In this metal working method, the deformation resistance of metal body or metal-containing ceramic body (hereinafter referred to simply as “metal body”) is lowered locally to thereby form low deformation resistance regions in the metal body, and shear deformation of the low deformation resistance regions is effected so as to fine the microstructure of metal body. In particular, the metal body is formed in unidirectionally drawn configuration so as to produce low deformation resistance regions crossing the metal body. Further, with respect to two non-low deformation resistance regions arranged to sandwich low deformation resistance region crossing the metal body, one non-low deformation resistance region is caused to have a relative position change to the other non-low deformation resistance region so as to effect shear deformation of the low deformation resistance region. The low deformation resistance regions can be moved along the direction of drawing of the metal body.

摘要翻译： 一种金属加工方法，其中金属体的微细结构细化，从而提高其强度，延展性或均匀性; 通过金属加工方法获得的金属体; 和通过金属加工方法得到的含金属陶瓷体。 在这种金属加工方法中，金属体或含金属陶瓷体（以下简称为“金属体”）的变形阻力局部地降低，从而在金属体中形成低变形阻力区域，并且低的剪切变形 实现变形阻力区域，以使金属体的微观结构细化。 特别地，金属体形成为单向拉伸构造，以便产生与金属体交叉的低变形阻力区域。 此外，对于与夹着与金属体交叉的低变形阻力区域配置的两个非低变形阻力区域，使一个非低变形阻力区域相对于另一非低变形阻力区域发生相对位置变化， 以实现低变形阻力区域的剪切变形。 低变形阻力区域可以沿着金属体的拉伸方向移动。