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    SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-ANGLE VIDEO SYSTEM
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-ANGLE VIDEO SYSTEM 有权
    半导体集成电路和多角度视频系统

    公开(公告)号：US20120105679A1

    公开(公告)日：2012-05-03

    申请号：US13274324

    申请日：2011-10-15

    Applicant: Hiroshi OSUGA ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

    Inventor： Hiroshi OSUGA ,  Takaaki Suzuki ,  Atsushi Kiuchi ,  Kazuhide Kawade ,  Hiroyuki Hamasaki

    IPC: H04N5/217 ,  H04N5/76

    CPC classification number: G06T5/006 ,  G06T2200/28 ,  G06T2207/10004 ,  H04N5/2173 ,  H04N5/23238 ,  H04N5/247 ,  H04N5/357 ,  H04N5/3572 ,  H04N5/77 ,  H04N5/907

    Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

    Abstract translation: 提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。 对于半导体集成电路，可以耦合多个摄像机和半导体存储器。 半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。 图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。 通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

    ATM cell processing apparatus
    4.
    发明授权
    ATM cell processing apparatus 失效
    ATM信元处理装置

    公开(公告)号：US06185212B2

    公开(公告)日：2001-02-06

    申请号：US09056770

    申请日：1998-04-08

    Applicant: Kenichi Sakamoto ,  Akio Makimoto ,  Akihiko Takase ,  Norihiko Moriwaki ,  Atsushi Kiuchi

    Inventor： Kenichi Sakamoto ,  Akio Makimoto ,  Akihiko Takase ,  Norihiko Moriwaki ,  Atsushi Kiuchi

    IPC: H04L1228

    CPC classification number: H04L49/254 ,  H04L49/30 ,  H04L2012/5681

    Abstract: An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.

    Abstract translation: 一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。 为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。 为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。 所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。 结果，可以形成具有大容量的快速电池缓冲器。 本单元缓冲器也可以应用于FIFO等。

    Digital peak and valley detector
    5.
    发明授权
    Digital peak and valley detector 失效
    数字峰谷检测器

    公开(公告)号：US4896104A

    公开(公告)日：1990-01-23

    申请号：US311161

    申请日：1989-02-15

    Applicant: Chandravadan N. Patel ,  Richard Wm. Blasco ,  Atsushi Kiuchi ,  Hiromitsu Inada

    Inventor： Chandravadan N. Patel ,  Richard Wm. Blasco ,  Atsushi Kiuchi ,  Hiromitsu Inada

    IPC: G06F7/02 ,  G01R19/04

    CPC classification number: G01R19/04

    Abstract: A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.

    Abstract translation: 数字峰谷检测器，包括峰值地址寄存器，谷值地址寄存器，峰值数据寄存器，谷值数据寄存器，用于将存储在峰值数据寄存器中的值与包含在其中的值数据进行比较的峰值比较器 数字信号施加到数字峰谷检测器，并使两个中的较大值存储在峰值数据寄存器中，同时将地址存储在峰值地址寄存器和谷比较器中，用于比较包含在 谷数值数据寄存器，其中包含在数字信号中的数值数据被加到数字峰谷检测器，用于确定哪一个较小，并且使两个中较小的值的值和地址分别存储在谷值数据中 和谷值地址寄存器。

    Information processing apparatus
    6.
    发明授权
    Information processing apparatus 失效
    信息处理装置

    公开(公告)号：US4809206A

    公开(公告)日：1989-02-28

    申请号：US87346

    申请日：1987-08-20

    Applicant: Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

    Inventor： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

    IPC: G06F9/34 ,  G06F7/544 ,  G06F12/02 ,  G06F17/10 ,  H03H17/02 ,  G06F7/38

    CPC classification number: G06F7/5443

    Abstract: This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.

    Abstract translation: 本发明涉及诸如数字信号处理器的信息处理设备，并且特别适用于数字滤波器。 从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中，并且通过地址运算单元的增量操作被依次读出。 数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算，进行数字信号处理。 该信息处理装置特别地具有如下装置：当访问地址从初始值开始时，由于增量操作而超过最终值并达到返回地址，自动将访问地址返回到初始值。 因此，可以重复使用存储在数据存储器中的多个数据。 为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值，进行了操作。

    Data processor and data processing system
    9.
    发明授权
    Data processor and data processing system 失效

    公开(公告)号：US07000140B2

    公开(公告)日：2006-02-14

    申请号：US09993704

    申请日：2001-11-27

    Applicant: Haruyasu Okubo ,  Atsushi Kiuchi ,  Shigezumi Matsui

    Inventor： Haruyasu Okubo ,  Atsushi Kiuchi ,  Shigezumi Matsui

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

    Abstract: This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the transition of the CPU to an instruction executable state is faster than in the standby mode and the lower power consumption than in the sleep mode is obtained.

    Data processer and data processing system
    10.
    发明授权
    Data processer and data processing system 失效

    公开(公告)号：US06542982B2

    公开(公告)日：2003-04-01

    申请号：US09783551

    申请日：2001-02-15

    Applicant: Yasuyuki Murakami ,  Shigezumi Matsui ,  Kunihiko Nishiyama ,  Atsushi Kiuchi ,  Yuichi Takitsune

    Inventor： Yasuyuki Murakami ,  Shigezumi Matsui ,  Kunihiko Nishiyama ,  Atsushi Kiuchi ,  Yuichi Takitsune

    IPC: G06F940

    CPC classification number: G06F9/3814 ,  G06F9/3802

    Abstract: In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

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