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公开(公告)号：US07138846B2
公开(公告)日：2006-11-21
申请号：US10322589
申请日：2002-12-19
IPC分类号： H03L5/00
CPC分类号： H01L29/812 , H01L27/0605 , H03K17/693
摘要： A field effect transistor switch circuit may include: (1) first, second, and third switch terminals; (2) a first field effect transistor, a pair of the main electrodes of which are connected respectively to the first switch terminal and the second switch terminal; and (3) a second field effect transistor, a pair of the main electrodes of which are connected respectively to the first switch terminal and the third switch terminal. A first resistor is connected between a control electrode and any one of the pair of the main electrodes of the first field effect transistor, and a second resistor is connected between a control electrode and any one of the pair of the main electrodes of the second field effect transistor.
摘要翻译： 场效应晶体管开关电路可以包括：（1）第一，第二和第三开关端子; （2）第一场效应晶体管，一对主电极分别连接到第一开关端子和第二开关端子; 和（3）第二场效应晶体管，其一对主电极分别连接到第一开关端子和第三开关端子。 第一电阻器连接在控制电极和第一场效应晶体管的一对主电极中的任一个之间，第二电阻器连接在控制电极和第二场的一对主电极中的任一个之间 效应晶体管。
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公开(公告)号：US20050017786A1
公开(公告)日：2005-01-27
申请号：US10864351
申请日：2004-06-10
申请人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
发明人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
IPC分类号： H03K17/00 , H03K17/0412 , H03K17/06 , H03K17/62 , H03K17/693
CPC分类号： H03K17/04123 , H03K17/693
摘要： Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
摘要翻译： 在串联连接的四个FET组成的四个开关电路部分设置在输出并输入高频信号的多个输入/输出端子之间。 栅极控制电压分别分别施加到四个FET的栅极端子，从而实现导通状态和截止状态。 在各开关电路部分中分别对漏极端子或FET的源极施加进一步的漏极控制电压，并且提供根据提供给每个开关电路部分的高频信号的电功率值的电压作为栅极控制电压 和漏极控制电压。
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公开(公告)号：US07173471B2
公开(公告)日：2007-02-06
申请号：US10864351
申请日：2004-06-10
申请人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
发明人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
IPC分类号： H03L5/00
CPC分类号： H03K17/04123 , H03K17/693
摘要： Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
摘要翻译： 在串联连接的四个FET组成的四个开关电路部分设置在输出并输入高频信号的多个输入/输出端子之间。 栅极控制电压分别分别施加到四个FET的栅极端子，从而实现导通状态和截止状态。 在各开关电路部分中分别对漏极端子或FET的源极施加进一步的漏极控制电压，并且提供根据提供给每个开关电路部分的高频信号的电功率值的电压作为栅极控制电压 和漏极控制电压。
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公开(公告)号：US07492238B2
公开(公告)日：2009-02-17
申请号：US11591462
申请日：2006-11-02
CPC分类号： H01P1/15 , H03K17/002 , H03K17/063 , H03K17/102 , H03K17/693
摘要： A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.
摘要翻译： 公共端子500经由电容器400连接到FET 101和102的漏极.FET 111至114串联连接，并且经由电容器401插入FET 101的源极和端子501之间。类似地，每个FET 121至124; FET 131〜133; FET 141〜143; FET 151〜153; 并且FET161〜163插入在FET101的源极或FET102与端子502〜506中的对应的一个之间。这种结构允许发送/接收路径的杂散电容值减小， 接收，从而获得有利的射频特性。
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公开(公告)号：US20060252394A1
公开(公告)日：2006-11-09
申请号：US11405447
申请日：2006-04-18
申请人： Atsushi Suwa , Tadayoshi Nakatsuka
发明人： Atsushi Suwa , Tadayoshi Nakatsuka
IPC分类号： H04B1/06
CPC分类号： H04B1/48
摘要： A switching circuit includes: an antenna terminal; a plurality of input/output terminals each for receiving and outputting a signal; and a plurality of basic switching sections each connected between the antenna terminal and an associated one of the input/output terminals. Each of the basic switching sections includes: a through switch formed by FETs connected in series; and a shunt switch. The sources of the FETs forming the through switch and the shunt switch are connected to a first potential fixing terminal through resistors. The resistor connected to the source of the FET at the first stage in the shunt switch is connected to a potential fixing terminal through a diode connected in the forward direction.
摘要翻译： 开关电路包括：天线端子; 多个输入/输出端子，用于接收和输出信号; 以及多个基本切换部，其各自连接在天线端子和相关联的输入/输出端子之间。 每个基本开关部分包括：由串联连接的FET构成的直通开关; 和分流开关。 形成贯通开关的FET和分流开关的源极通过电阻器连接到第一电位固定端子。 在并联开关的第一级连接到FET的源极的电阻器通过沿正向连接的二极管连接到电位固定端子。
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公开(公告)号：US20070103252A1
公开(公告)日：2007-05-10
申请号：US11591462
申请日：2006-11-02
IPC分类号： H01P1/15
CPC分类号： H01P1/15 , H03K17/002 , H03K17/063 , H03K17/102 , H03K17/693
摘要： A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.
摘要翻译： 公共端子500经由电容器400连接到FET 101和102的漏极.FET 111至114串联连接，并且经由电容器401插入FET 101的源极和端子501之间。类似地，每个FET 121至124; FET 131〜133; FET 141〜143; FET 151〜153; 并且FET161〜163插入在FET101的源极或FET102与端子502〜506中的对应的一个之间。这种结构允许发送/接收路径的杂散电容值减小， 接收，从而获得有利的射频特性。
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7.发明授权High-frequency switch circuit and mobile telecommunications terminal device using the same 失效高频开关电路和移动电信终端设备使用相同公开(公告)号：US07020453B2
公开(公告)日：2006-03-28
申请号：US10489816
申请日：2003-05-21
IPC分类号： H04B1/28
CPC分类号： H04W52/029 , H04B1/1615 , H04B1/44 , H04B1/48 , H04W52/0274 , Y02D70/1222 , Y02D70/40
摘要： An object is to provide an antenna switch semiconductor integrated circuit which reduces a consumption current. To this end, of two control input signals which are fed to a logic circuit which controls turning on and off of a plurality of switching FETs, a control input signal for switching between a sending mode and a receiving mode is fed to an oscillation circuit, thereby making the oscillation circuit operate only during the sending mode under which the logic circuit needs a high voltage. A voltage raising circuit accordingly operates, whereby a raised voltage is supplied to the logic circuit. During the receiving mode, the oscillation circuit stops, and the voltage raising circuit stops. With a switch turned on using the logic circuit, a power source voltage is supplied directly to the logic circuit when the voltage raising circuit is not in operation. This shortens the operation time of the voltage raising circuit and reduces the consumption current.
摘要翻译： 目的在于提供减少消耗电流的天线开关半导体集成电路。 为此，由馈送到控制多个开关FET的导通和截止的逻辑电路的两个控制输入信号，将用于在发送模式和接收模式之间切换的控制输入信号馈送到振荡电路， 从而使振荡电路仅在逻辑电路需要高电压的发送模式下工作。 升压电路相应地工作，由此向逻辑电路提供升高的电压。 在接收模式下，振荡电路停止，升压电路停止。 当使用逻辑电路接通开关时，当升压电路不工作时，将电源电压直接提供给逻辑电路。 这缩短了升压电路的工作时间，降低了消耗电流。
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8.发明申请Antenna switch circuit, and composite high frequency part and mobile communication device using the same 审中-公开天线开关电路，复合高频部分和移动通信装置使用相同公开(公告)号：US20050231439A1
公开(公告)日：2005-10-20
申请号：US11103550
申请日：2005-04-12
申请人： Atsushi Suwa , Tadayoshi Nakatsuka
发明人： Atsushi Suwa , Tadayoshi Nakatsuka
IPC分类号： H03K17/693 , H01P1/15 , H01Q3/24 , H04B1/40
CPC分类号： H01P1/15
摘要： First and second through-side field effect transistors are connected between first and second high frequency signal input/output terminals, and an antenna, respectively. The first and the second high frequency signal input/output terminals are connected with one end of the first and the second shunt-side field effect transistors, respectively. A series resonant circuit including a shunt capacitor and a bonding wire is connected between the other end of the first and the second shunt-side field effect transistors, and a ground.
摘要翻译： 第一和第二通过侧场效应晶体管分别连接在第一和第二高频信号输入/输出端子和天线之间。 第一和第二高频信号输入/输出端分别与第一和第二分流侧场效应晶体管的一端连接。 包括分流电容器和接合线的串联谐振电路连接在第一和第二分路侧场效应晶体管的另一端和地之间。
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公开(公告)号：US20100117763A1
公开(公告)日：2010-05-13
申请号：US12528070
申请日：2008-02-19
申请人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
发明人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
摘要： A bandpass filter includes a combination of a BAW filter and a patterned planar filter with stubs. The BAW filter is composed of a plurality of piezoelectric resonators to give a specific frequency bandpass, while the planer filter is configured to attenuate frequencies near and outside the bandpass. The resonators are connected in a ladder configuration between a first signal transmission path and a ground. The planar filter includes a strip line formed on a dielectric layer to define a second signal transmission path. The BAW filter and the planar filter are formed on a common substrate with the first and second transmission paths connected to each other. The BAW filter, in combination with the patterned planar filter added with the stub, can improve a deep near-band rejection inherent to the BAW filter, exhibiting an excellent out-of-band rejection over certain adjacent frequency ranges outside of the bandpass, and therefore give a sharp and wide bandpass.
摘要翻译： 带通滤波器包括BAW滤波器和具有短截线的图案化平面滤波器的组合。 BAW滤波器由多个压电谐振器组成，以提供特定的频带通量，而平面滤波器被配置为衰减带通附近和外的频率。 谐振器以第一信号传输路径和地之间的梯形结构连接。 平面滤波器包括形成在电介质层上以限定第二信号传输路径的带状线。 BAW滤波器和平面滤波器形成在公共基板上，其中第一和第二传输路径彼此连接。 BAW滤波器与添加有短截线的图形平面滤波器组合可以改善BAW滤波器固有的深近带阻抗，在带通外的某些相邻频率范围内表现出优异的带外抑制，以及 因此给出一个清晰而宽广的带通。
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公开(公告)号：US08098118B2
公开(公告)日：2012-01-17
申请号：US12528070
申请日：2008-02-19
申请人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
发明人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
摘要： A bandpass filter includes a combination of a BAW filter and a patterned planar filter with stubs. The BAW filter is composed of a plurality of piezoelectric resonators to give a specific frequency bandpass, while the planer filter is configured to attenuate frequencies near and outside the bandpass. The resonators are connected in a ladder configuration between a first signal transmission path and a ground. The planar filter includes a strip line formed on a dielectric layer to define a second signal transmission path. The BAW filter and the planar filter are formed on a common substrate with the first and second transmission paths connected to each other. The BAW filter, in combination with the patterned planar filter added with the stub, can improve a deep near-band rejection inherent to the BAW filter, exhibiting an excellent out-of-band rejection over certain adjacent frequency ranges outside of the bandpass, and therefore give a sharp and wide bandpass.
摘要翻译： 带通滤波器包括BAW滤波器和具有短截线的图案化平面滤波器的组合。 BAW滤波器由多个压电谐振器组成，以提供特定的频带通量，而平面滤波器被配置为衰减带通附近和外的频率。 谐振器以第一信号传输路径和地之间的梯形结构连接。 平面滤波器包括形成在电介质层上以限定第二信号传输路径的带状线。 BAW滤波器和平面滤波器形成在公共基板上，其中第一和第二传输路径彼此连接。 BAW滤波器与添加有短截线的图形平面滤波器组合可以改善BAW滤波器固有的深近带阻抗，在带通外的某些相邻频率范围内表现出优异的带外抑制，以及 因此给出一个清晰而宽广的带通。
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