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1.
公开(公告)号:US08832478B2
公开(公告)日:2014-09-09
申请号:US13282896
申请日:2011-10-27
申请人: Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
发明人: Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
IPC分类号: G06F1/32
CPC分类号: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
摘要: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括具有多个域的处理器,至少包括对于操作系统(OS)是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来,处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外,可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。
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公开(公告)号:US20130111120A1
公开(公告)日:2013-05-02
申请号:US13282896
申请日:2011-10-27
申请人: Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
发明人: Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
CPC分类号: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
摘要: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括具有多个域的处理器,至少包括对于操作系统(OS)是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来,处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外,可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。
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公开(公告)号:US08943340B2
公开(公告)日:2015-01-27
申请号:US13285414
申请日:2011-10-31
申请人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells , Nadav Shulman
发明人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells , Nadav Shulman
CPC分类号: G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/3885 , Y02D10/126 , Y02D10/152 , Y02D10/171
摘要: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括具有功率控制器以控制处理器工作频率的多核处理器。 更具体地,功率控制器可以将处理器的最大工作频率限制在小于配置的最大工作频率,以便能够减少响应于电力状态事件而发生的频率转换的数量,从而避免在处理这些操作时所执行的操作的开销 转换 描述和要求保护其他实施例。
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4.
公开(公告)号:US20130111236A1
公开(公告)日:2013-05-02
申请号:US13282947
申请日:2011-10-27
申请人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
发明人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
IPC分类号: G06F1/32
CPC分类号: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
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公开(公告)号:US20130111226A1
公开(公告)日:2013-05-02
申请号:US13285414
申请日:2011-10-31
申请人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells , Nadav Shulman
发明人: Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells , Nadav Shulman
IPC分类号: G06F1/00
CPC分类号: G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/3885 , Y02D10/126 , Y02D10/152 , Y02D10/171
摘要: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
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6.
公开(公告)号:US20130111121A1
公开(公告)日:2013-05-02
申请号:US13285465
申请日:2011-10-31
申请人: Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Wiessman , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
发明人: Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Wiessman , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
CPC分类号: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
摘要: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。 处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。 描述和要求保护其他实施例。
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