公开(公告)号：US10128296B2

公开(公告)日：2018-11-13

申请号：US14591873

申请日：2015-01-07

Applicant: BAE Systems Imaging Solutions Inc.

Inventor： Boyd Fowler

IPC: H01L27/146 ,  H04N5/355

Abstract: A pixel sensor having a main photodiode and a parasitic photodiode and a method for reading out that pixel sensor are disclosed. The parasitic photodiode also serves the function of a floating diffusion node in the pixel. The pixel sensor is read by first determining the exposure as measured by the parasitic photodiode and then determining the exposure as read by the main photodiode. One of the two exposure measurements is chosen as the pixel output. The main photodiode has a light conversation efficiency chosen such that one of the two measurements will provide a measurement of the exposure over a dynamic range that is greater than that of either the main photodiode or the parasitic photodiode utilized separately.

公开(公告)号：US20140300389A1

公开(公告)日：2014-10-09

申请号：US13856402

申请日：2013-04-03

Applicant: BAE SYSTEMS IMAGING SOLUTIONS, INC.

Inventor： Boyd Fowler ,  Peter Bartkovjak

IPC: H03K5/1252 ,  H03K17/16

CPC classification number: H03K5/1252 ,  G11C27/026

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract translation: 公开了采样保持电路和采样信号的方法。 采样和保持电路包括第一和第二开关，第一，第二和第三电容器以及放大器。 放大器接收要在第一输入上采样的信号。 第一电容器的特征在于第一电容，并且具有通过第一开关连接到放大器的输出端的第一端子。 第二电容器的特征在于第二电容，并且具有通过第二开关连接到放大器的输出端的第二端子。 第三电容器连接第一和第二端子。 当第一开关处于非导通状态并且第二开关处于导通状态时，放大器被配置为形成具有作为反馈电路的第三电容器的电容跨阻放大器。

公开(公告)号：US20150122974A1

公开(公告)日：2015-05-07

申请号：US14591873

申请日：2015-01-07

Applicant: BAE Systems Imaging Solutions Inc.

Inventor： Boyd Fowler

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14656 ,  H04N5/35563

Abstract: A pixel sensor having a main photodiode and a parasitic photodiode and a method for reading out that pixel sensor are disclosed. The parasitic photodiode also serves the function of a floating diffusion node in the pixel. The pixel sensor is read by first determining the exposure as measured by the parasitic photodiode and then determining the exposure as read by the main photodiode. One of the two exposure measurements is chosen as the pixel output. The main photodiode has a light conversation efficiency chosen such that one of the two measurements will provide a measurement of the exposure over a dynamic range that is greater than that of either the main photodiode or the parasitic photodiode utilized separately.

Abstract translation: 公开了具有主光电二极管和寄生光电二极管的像素传感器以及读出该像素传感器的方法。 寄生光电二极管还用于像素中的浮动扩散节点的功能。 通过首先确定由寄生光电二极管测量的曝光，然后确定由主光电二极管读取的曝光来读取像素传感器。 选择两个曝光测量中的一个作为像素输出。 主光电二极管具有选择的光对话效率，使得两个测量中的一个将提供在大于分开使用的主光电二极管或寄生光电二极管的动态范围上的曝光的测量。

公开(公告)号：US20140333808A1

公开(公告)日：2014-11-13

申请号：US13892178

申请日：2013-05-10

Applicant: BAE SYSTEMS IMAGING SOLUTIONS, INC.

Inventor： Boyd Fowler ,  Xinqiao Liu

IPC: H04N5/335

CPC classification number: H04N5/3745 ,  H04N5/37452 ,  H04N5/378

Abstract: An image sensor that includes a first imaging array and a FPGA processor that processes images captured by the imaging array to provide information about the scene projected on the first imaging array is disclosed. The FPGA processor is connected to the first imaging array and includes an interface for receiving images from the first imaging array and an interface to an image storage memory that stores a plurality of images. The FPGA implements a plurality of image processing functions in the gates of the FPGA. The image processing functions processing one of the images stored in the image storage memory to extract a quantity related to the one of the images. The FPGA also includes an I/O interface used by the FPGA to output the quantity to a device external to the image sensor.

Abstract translation: 公开了一种图像传感器，其包括第一成像阵列和FPGA处理器，其处理由成像阵列拍摄的图像以提供关于投影在第一成像阵列上的场景的信息。 FPGA处理器连接到第一成像阵列，并且包括用于从第一成像阵列接收图像的接口和存储多个图像的图像存储存储器的接口。 FPGA在FPGA的门中实现多个图像处理功能。 图像处理功能处理存储在图像存储存储器中的图像之一，以提取与该图像之一相关的数量。 FPGA还包括FPGA使用的I / O接口，将数量输出到图像传感器外部的设备。

公开(公告)号：US10123762B2

公开(公告)日：2018-11-13

申请号：US14988623

申请日：2016-01-05

Applicant: BAE Systems Imaging Solutions Inc.

Inventor： Xinqiao Liu ,  Boyd Fowler

IPC: A61B6/00 ,  A61B6/14 ,  G01T1/02

Abstract: An x-ray imaging system and a method for retrofitting existing x-ray generators to allow those generators to be controlled by a digital x-ray imaging system are disclosed. The x-ray imaging system includes an imaging array and an image controller. The imaging array is configured to be positioned within a patient's mouth, the imaging array acquiring an image of the patient's teeth when the patient's head is illuminated with x-rays. The imaging array includes an x-ray dosimeter that provides an x-ray exposure signal indicative of an x-ray exposure received by the imaging array. The image controller is coupled to the imaging array and receives the x-ray exposure signal, the image controller includes a first wireless link that controls an x-ray generator by initiating a pre-programmed x-ray exposure. The wireless controllable switch can be used to replace an existing manually controlled switch in an existing x-ray generator.

公开(公告)号：US09374545B2

公开(公告)日：2016-06-21

申请号：US14026855

申请日：2013-09-13

Applicant: BAE Systems Imaging Solutions, Inc.

Inventor： Boyd Fowler ,  Hung Do ,  Xinqiao Liu

IPC: H04N5/3745 ,  H03F3/16 ,  H03F3/08

CPC classification number: H04N5/3745 ,  H03F3/082 ,  H03F3/16 ,  H04N5/357 ,  H04N5/378

Abstract: A column readout amplifier and imaging array using the same method are disclosed. The column readout amplifier includes a signal amplifier having an amplifier signal output, a first filter capacitor, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, and a switching network. The switching network connects the amplifier signal output to the buffer amplifier input and the buffer amplifier output to the first filter capacitor during a first time period, and connects the amplifier signal output directly to the first filter capacitor during a second time period. The time periods can be of fixed duration or determined by the difference in potential between the input and output of the buffer amplifier. The column readout amplifier can be used in an imaging array to readout columns of pixels.

Abstract translation: 公开了使用相同方法的列读出放大器和成像阵列。 列读出放大器包括具有放大器信号输出的信号放大器，第一滤波电容器，具有缓冲放大器输入和缓冲放大器输出的缓冲放大器以及开关网络。 开关网络在第一时间段内将放大器信号输出连接到缓冲放大器输入和缓冲放大器输出到第一滤波电容器，并且在第二时间段内将放大器信号输出直接连接到第一滤波电容器。 时间段可以是固定持续时间，或由缓冲放大器的输入和输出之间的电位差决定。 列读出放大器可用于成像阵列中以读出像素列。

公开(公告)号：US09253396B2

公开(公告)日：2016-02-02

申请号：US14097162

申请日：2013-12-04

Applicant: BAE Systems Imaging Solutions Inc.

Inventor： Hung T. Do ,  Peter Bartkovjak ,  Boyd Fowler ,  Stephen W. Mims

IPC: H04N5/3745 ,  H04N5/232

CPC classification number: H04N5/23232 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/37455 ,  H04N5/378

Abstract: An imaging sensor using a novel bit line processing circuit, that circuit, and the method of processing the pixel outputs from an image sensor using that processing circuit are disclosed. The image sensor includes an array of pixel sensors, a signal digitizing circuit, and a digitizing controller. Each pixel sensor generates a voltage signal that is a function of a charge on the photodetector in that pixel sensor, and couples that voltage signal to a bit line in response to a first signal. The signal digitizing circuit is connected to the bit line, the digitizing circuit converting the voltage signal to a plurality of output digital values, the output digital values having selectable levels of digitization noise. The digitizing controller generates the level of noise based on the voltage signal. The signal digitizing circuit includes a variable gain amplifier and an ADC having a fixed number of bits.

Abstract translation: 公开了一种利用新颖的位线处理电路，该电路以及使用该处理电路从图像传感器处理像素输出的方法的成像传感器。 图像传感器包括像素传感器阵列，信号数字化电路和数字化控制器。 每个像素传感器产生作为该像素传感器中的光电检测器上的电荷的函数的电压信号，并且响应于第一信号将该电压信号耦合到位线。 信号数字化电路连接到位线，数字化电路将电压信号转换为多个输出数字值，输出数字值具有可选择的数字化噪声水平。 数字化控制器基于电压信号产生噪声电平。 信号数字化电路包括可变增益放大器和具有固定位数的ADC。

公开(公告)号：US20150076321A1

公开(公告)日：2015-03-19

申请号：US14026855

申请日：2013-09-13

Applicant: BAE Systems Imaging Solutions, Inc.

Inventor： Boyd Fowler ,  Hung Do ,  Xinqiao Liu

IPC: H04N5/3745 ,  H03F3/16

CPC classification number: H04N5/3745 ,  H03F3/082 ,  H03F3/16 ,  H04N5/357 ,  H04N5/378

Abstract: A column readout amplifier and imaging an-ay using the same method are disclosed. The column readout amplifier includes a signal amplifier having an amplifier signal output, a first filter capacitor, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, and a switching network. The switching network connects the amplifier signal output to the buffer amplifier input and the buffer amplifier output to the first filter capacitor during a first time period, and connects the amplifier signal output directly to the first filter capacitor during a second time period. The time periods can be of fixed duration or determined by the difference in potential between the input and output of the buffer amplifier. The column readout amplifier can be used in an imaging array to readout columns of pixels.

Abstract translation: 公开了使用相同方法的列读出放大器和成像原理。 列读出放大器包括具有放大器信号输出的信号放大器，第一滤波电容器，具有缓冲放大器输入和缓冲放大器输出的缓冲放大器以及开关网络。 开关网络在第一时间段内将放大器信号输出连接到缓冲放大器输入和缓冲放大器输出到第一滤波电容器，并且在第二时间段内将放大器信号输出直接连接到第一滤波电容器。 时间段可以是固定持续时间，或由缓冲放大器的输入和输出之间的电位差决定。 列读出放大器可用于成像阵列中以读出像素列。

公开(公告)号：US08952729B2

公开(公告)日：2015-02-10

申请号：US13856402

申请日：2013-04-03

Applicant: BAE Systems Imaging Solutions, Inc.

Inventor： Boyd Fowler ,  Peter Bartkovjak

IPC: H03K5/00 ,  H03K5/1252 ,  H03K17/16

CPC classification number: H03K5/1252 ,  G11C27/026

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract translation: 公开了采样保持电路和采样信号的方法。 采样和保持电路包括第一和第二开关，第一，第二和第三电容器以及放大器。 放大器接收要在第一输入上采样的信号。 第一电容器的特征在于第一电容，并且具有通过第一开关连接到放大器的输出端的第一端子。 第二电容器的特征在于第二电容，并且具有通过第二开关连接到放大器的输出端的第二端子。 第三电容器连接第一和第二端子。 当第一开关处于非导通状态并且第二开关处于导通状态时，放大器被配置为形成具有作为反馈电路的第三电容器的电容跨阻放大器。

公开(公告)号：US10277838B2

公开(公告)日：2019-04-30

申请号：US15222786

申请日：2016-07-28

Applicant: BAE Systems Imaging Solutions Inc.

Inventor： Xinqiao Liu ,  Boyd Fowler

IPC: H04N5/33 ,  H04N5/374 ,  H04N5/378 ,  H01L27/146 ,  H01L31/0232

Abstract: An imaging array and method for fabricating the same are disclosed. The imaging array includes a semiconductor substrate having a plurality of VIS pixel sensors and a plurality of SWIR readout circuits fabricated therein. An insulating layer is deposited on the semiconductor substrate. The insulating array has wells overlying the SWIR pixel sensors. A plurality of SWIR photodiodes are deposited in the wells. Each SWIR photodiode is located in a corresponding one of the wells and is connected by an electrically conducting path with the SWIR readout circuit underlying the SWIR photodiode. An electrically conducting transparent electrode overlying the SWIR photodiodes is connected to each of the SWIR photodiodes.