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公开(公告)号：US20240242659A1
公开(公告)日：2024-07-18
申请号：US18005373
申请日：2021-11-24
发明人： Li XIAO , Seungwoo HAN , Dongni LIU , Haoliang ZHENG , Minghua XUAN , Jiao ZHAO , Liang CHEN , Xiaorong CUI
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2300/0861 , G09G2310/0251 , G09G2310/0262 , G09G2310/0297
摘要： A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.
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2.发明公开公开(公告)号：US20240221608A1
公开(公告)日：2024-07-04
申请号：US17923690
申请日：2021-11-29
发明人： Seungwoo HAN , Haoliang ZHENG , Dongni LIU , Li XIAO , Jiao ZHAO , Xiaorong CUI , Minghua XUAN
CPC分类号： G09G3/32 , G11C19/28 , G09G2300/0842 , G09G2300/0861 , G09G2310/0286 , G09G2310/08
摘要： A shift register includes: an input circuit configured to receive an input signal; a first control circuit configured to control, in response to a second clock signal and a voltage at a second node, a voltage at the first node; a second control circuit configured to control, in response to a first clock signal, the second clock signal, and the voltage at the first node, a voltage at the second node, and control, in response to the second clock signal and the voltage at the first node, a voltage at the fifth node; and an output circuit configured to transmit, in response to an active level at the first node, a second power signal to an output signal terminal, and transmit, in response to an active level at the fifth node, the first power signal to the output signal terminal. All transistors included in the shift register are N-type transistors.
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公开(公告)号：US20240257772A1
公开(公告)日：2024-08-01
申请号：US18290924
申请日：2022-09-05
发明人： Yuzhen GUO , Haoliang ZHENG , Minghua XUAN , Hebin ZHAO , Meirong LU , Chenyang ZHANG , Li XIAO , Xiaorong CUI , Jiao ZHAO , Shulei LI , Weixing LIU , Jintao PENG , Chunfang ZHANG , Xinxing WANG , Zhiqiang XU , Wanpeng TENG , Kai GUO
IPC分类号： G09G3/34 , G02F1/167 , G02F1/16756 , G02F1/16766 , G02F1/1677
CPC分类号： G09G3/344 , G02F1/167 , G02F1/16756 , G02F1/16766 , G02F1/1677
摘要： A display panel, a method for driving a display panel, and a display apparatus are provided. The display panel includes a first base substrate and a plurality of pixels on one side of the first base substrate. Each pixel includes: a plurality of pixel sub-electrodes independent from each other and configured to form an electric field with an included angle greater than 0 with respect to a direction perpendicular to the first base substrate under control of incompletely same driving signals; a common electrode on a side of the pixel electrode away from the first base substrate; and an electrophoretic liquid layer between the pixel electrode and the common electrode, including a plurality of charged particles therein.
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公开(公告)号：US20240096288A1
公开(公告)日：2024-03-21
申请号：US18274470
申请日：2021-12-20
发明人： Haoliang ZHENG , Yan QU , Dongni LIU , Li XIAO , Jiao ZHAO , Xiaorong CUI , Seungwoo HAN , Minghua XUAN
IPC分类号： G09G3/3275 , G09G3/3266
CPC分类号： G09G3/3275 , G09G3/3266 , G09G2310/0297 , G09G2310/061 , G09G2310/08
摘要： A display substrate a driving method therefor, and a display apparatus. The display substrate comprises: M rows and N columns of sub-pixels, N data signal lines and a data reset circuit, wherein at least one sub-pixel comprises a pixel circuit; an ith data signal line is connected to pixel circuits in an ith column, where M≥1, N≥1, and 1≤i≤N; and the data reset circuit is electrically connected to a data reset control end, a data initial signal end and the N data signal lines, and is configured to provide a signal of the data initial signal end to the N data signal lines under the control of the data reset control end.
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