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公开(公告)号：US20190086755A1
公开(公告)日：2019-03-21
申请号：US15941271
申请日：2018-03-30
发明人： Maokun TIAN , Zhonghao HUANG , Xu WU
IPC分类号： G02F1/1362 , G02F1/1333 , G02F1/1343 , H01L27/12
CPC分类号： G02F1/136286 , G02F1/133345 , G02F1/13439 , G02F2201/121 , G02F2201/123 , H01L27/124
摘要： The present disclosure provides an array substrate, a method for manufacturing the same, and a display device, which belongs to the field of display technology. The array substrate includes a metal electrode layer, a pad layer, a first insulating layer and a first transparent conductive layer, wherein: the pad layer includes a transparent conductive material, the metal electrode layer includes a conductive layer and protection layers formed on both surfaces of the conductive layer, and the pad layer is connected to the metal electrode layer; the first insulating layer is covered on the metal electrode layer and the pad layer, and the first transparent conductive layer is disposed on the first insulating layer; and a via hole is provided in the first insulating layer, and the first transparent conductive layer is connected to the pad layer through the via hole.
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公开(公告)号：US20220293035A1
公开(公告)日：2022-09-15
申请号：US17551368
申请日：2021-12-15
发明人： Zhiyong NING , Zhonghao HUANG , Xu WU , Kunkun GAO , Chao ZHANG , Can WANG , Maokun TIAN
摘要： A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.
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公开(公告)号：US20190115374A1
公开(公告)日：2019-04-18
申请号：US16086278
申请日：2018-02-07
发明人： Xu WU , Rong WU , Chao ZHANG , Zhonghao HUANG
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66 , G02F1/1368 , G02F1/1343 , G02F1/1362
摘要： A method for manufacturing an array substrate includes: forming a metal-oxide semiconductor layer, a first conductive layer and a second conductive layer sequentially on a substrate; and treating the metal-oxide semiconductor layer, the first conductive layer and the second conductive layer in a single patterning process using a mask, to form an active layer, pixel electrodes, a source drain pattern layer which includes source electrodes, drain electrodes and data lines, and a reserved pattern of the first conductive layer which is provided in a same layer as the pixel electrodes and formed on sides of the source electrodes and the data lines close to the active layer. The drain electrode is in direct contact with the pixel electrode, and a partial region of the pixel electrode is unobstructed from the drain electrode.
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4.发明申请公开(公告)号：US20220344377A1
公开(公告)日：2022-10-27
申请号：US17432105
申请日：2021-02-01
发明人： Zhiyong NING , Zhonghao HUANG , Chao ZHANG , Zhaojun WANG , Hongru ZHOU , Yutong YANG , Rui WANG , Xu WU , Kunkun GAO
IPC分类号： H01L27/12
摘要： A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.
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公开(公告)号：US20190187505A1
公开(公告)日：2019-06-20
申请号：US16322793
申请日：2018-05-10
发明人： Wei SHEN , Yongliang ZHAO , Xu WU , Houfeng ZHOU , Zhiyong NING
IPC分类号： G02F1/1362 , H01L27/092 , H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： G02F1/13624 , G02F2001/136245 , H01L27/092 , H01L27/124 , H01L29/41733 , H01L29/66742 , H01L29/786
摘要： A thin film transistor, a controlling method thereof, an array substrate and a display device. The thin film transistor includes: a substrate; and a gate electrode, an active layer, a source and a drain on the substrate. The source comprises two source electrodes electrically connected with each other; the drain comprises two drain electrodes electrically connected with each other, and the two drain electrodes are between the two source electrodes; and the active layer comprises primary channels between adjacent source electrodes and drain electrodes and a secondary channel between the two drain electrodes.
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公开(公告)号：US20220057679A1
公开(公告)日：2022-02-24
申请号：US17241140
申请日：2021-04-27
发明人： Maokun TIAN , Zhonghao HUANG , Xu WU , Chengjun QI , Jun WANG , Dan LIU
IPC分类号： G02F1/1362 , H01L27/12
摘要： An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.
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公开(公告)号：US20210074735A1
公开(公告)日：2021-03-11
申请号：US16633637
申请日：2019-01-07
发明人： Hongru ZHOU , Zhonghao HUANG , Xu WU , Chao ZHANG , Kai WANG
摘要： A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The thin film transistor is provided on a base substrate and includes: an active layer including a first surface and a second surface which are opposite to each other, in which the second surface is closer to the base substrate than the first surface; and a source-drain electrode layer including a source electrode and a drain electrode which are separated from each other and are respectively connected with the active layer; each of the first surface and the second surface is a non-flat surface, and the non-flat surface includes a plurality of depressions and a plurality of protrusions which are alternately arranged.
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