-
公开(公告)号：US11700688B2
公开(公告)日：2023-07-11
申请号：US17183909
申请日：2021-02-24
Inventor： Yongchao Huang , Qinghe Wang , Haitao Wang , Jun Liu , Jun Cheng , Ce Zhao , Liangchen Yan
CPC classification number: H05K1/09 , H05K3/04 , H05K2201/10128
Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes a first conductive line extending in a first direction on a base substrate, a second conductive line extending in a second direction crossing the first direction on the base substrate, and an insulation layer arranged between the first conductive line and the second conductive line. The display substrate further includes a buffer layer arranged between the first conductive line and the base substrate, a groove extending in the first direction is formed in the buffer layer, the first conductive line is arranged in the groove, and a surface of the first conductive line away from the base substrate is flush with a surface of the buffer layer away from the base substrate.
-
公开(公告)号：US20190221588A1
公开(公告)日：2019-07-18
申请号：US15580240
申请日：2017-06-23
Inventor： Tongshang Su , Jun Cheng , Ce Zhao , Bin Zhou , Dongfang Wang , Guangcai Yuan
IPC: H01L27/12 , G09G3/3283 , G09G3/3291 , G02F1/133
Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
-
3.发明申请公开(公告)号：US20190157308A1
公开(公告)日：2019-05-23
申请号：US16030825
申请日：2018-07-09
Inventor： Yuankui Ding , Guangcai Yuan , Ce Zhao , Bin Zhou , Jun Cheng , Zhaofan Liu , Yingbin Hu , Yongchao Huang
IPC: H01L27/12 , H01L29/786 , H01L21/027 , G03F7/16 , G03F7/20 , G03F7/26 , G03F7/42 , G03F7/038
Abstract: A method of manufacturing an array substrate assembly, an array substrate assembly manufactured by the method, and a display panel including the array substrate assembly are disclosed. The method includes: providing a substrate, the substrate having a first region as a preset semiconductor-removed region, and a second region as a remaining region; forming, in the first region of the substrate, a semiconductor removing layer corrodible by a corrosive solution; and forming a semiconductor layer on the substrate formed with the semiconductor removing layer, so that the semiconductor layer covers the semiconductor removing layer.
-
公开(公告)号：US10230073B2
公开(公告)日：2019-03-12
申请号：US15321154
申请日：2016-02-26
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wulin Shen , Jun Cheng
IPC: H01L51/52
Abstract: The present invention provides an organic light-emitting display panel, comprising: a substrate; a light-emitting unit provided on the substrate; and a package structure covering the light-emitting unit. The organic light-emitting display panel further comprises a thermally conductive structure, and the thermally conductive structure is at a side of the light-emitting unit far away from the substrate. Correspondingly, the present invention further provides a display device. The thermally conductive structure provided by the present invention can rapidly dissipate the heat generated by the light-emitting unit, so that the organic light-emitting display panel has an improved performance and the display device has an extended service life.
-
公开(公告)号：US09793327B2
公开(公告)日：2017-10-17
申请号：US15037883
申请日：2015-12-10
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jun Cheng
CPC classification number: H01L27/3248 , H01L27/124 , H01L27/3262 , H01L27/3267 , H01L27/3276 , H01L2227/323 , H01L2251/5323
Abstract: The present application discloses an array substrate comprising a pixel unit comprising a bottom emitting organic light emitting diode, a top emitting organic light emitting diode, a first drive thin film transistor, and a second drive thin film transistor. The first drive thin film transistor is connected to the bottom emitting organic light emitting diode for driving the bottom emitting organic light emitting diode to emit light. The second drive thin film transistor is connected to the top emitting organic light emitting diode for driving the top emitting organic light emitting diode to emit light.
-
Patent Agency Ranking
公开(公告)号：US20170077201A1
公开(公告)日：2017-03-16
申请号：US15122172
申请日：2015-09-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiangbo Chen , Jun Cheng , Chunsheng Jiang , Xiaodi Liu , Xiangyong Kong
CPC classification number: H01L27/3262 , H01L21/77 , H01L27/1288 , H01L51/56 , H01L2227/323
Abstract: Embodiments of the invention provide an array substrate and a method of manufacturing the same. The method comprises: forming a gate electrode pattern, a gate insulation layer, an active layer pattern and an etching stopping layer on a substrate; forming a photoresist layer on the etching stopping layer; performing a single patterning process on the photoresist layer, such that photoresist in the first region is partially etched off, photoresist in the second region is completely etched off, and photoresist in the third region is completely remained; and performing a single etching process, such that residual photoresist in the first region and a portion of the etching stopping layer in the first region are etched off, and at the same time, a portion of the etching stopping layer and a portion of the gate insulation layer in the second region are etched off.
Abstract translation: 本发明的实施例提供阵列基板及其制造方法。 该方法包括：在衬底上形成栅极电极图案，栅极绝缘层，有源层图案和蚀刻停止层; 在所述蚀刻停止层上形成光致抗蚀剂层; 在光致抗蚀剂层上执行单一的图案化工艺，使得第一区域中的光致抗蚀剂被部分蚀刻掉，第二区域中的光致抗蚀剂被完全蚀刻掉，并且第三区域中的光致抗蚀剂被完全残留; 并进行单蚀刻处理，使得第一区域中的残留光致抗蚀剂和第一区域中的蚀刻停止层的一部分被蚀刻掉，同时蚀刻停止层的一部分和栅极的一部分 第二区域中的绝缘层被蚀刻掉。
-
7.发明申请PIXEL UNIT AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE 有权像素单元及其制造方法，阵列基板和显示设备公开(公告)号：US20150129881A1
公开(公告)日：2015-05-14
申请号：US14361700
申请日：2013-11-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiangyong Kong , Dongfang Wang , Jun Cheng , Hongda Sun
IPC: H01L27/12
CPC classification number: H01L27/1248 , G02F1/136227 , H01L27/1244 , H01L27/1288
Abstract: The present invention provides a pixel unit including a thin film transistor and a pixel electrode, the thin film transistor includes a gate, a source and a drain, and the pixel electrode is electrically connected to the drain through a via hole. An upper end surface of the via hole is connected to the pixel electrode, and a lower end surface of the via hole is connected to the drain. The via hole is a step-shaped hole, and an area of the upper end surface of the via hole is larger than that of the lower end surface of the via hole. The present invention also provides a method of fabricating the pixel unit, an array substrate including the pixel unit, and a display device including the array substrate.
Abstract translation: 本发明提供一种包括薄膜晶体管和像素电极的像素单元，薄膜晶体管包括栅极，源极和漏极，并且像素电极通过通孔电连接到漏极。 通孔的上端面与像素电极连接，通孔的下端面与漏极连接。 通孔是台阶状的孔，通孔的上端面的面积大于通孔的下端面的面积。 本发明还提供一种制造像素单元的方法，包括该像素单元的阵列基板以及包括该阵列基板的显示装置。
-
8.发明授权公开(公告)号：US12237422B2
公开(公告)日：2025-02-25
申请号：US17765238
申请日：2021-05-20
Inventor： Qinghe Wang , Tongshang Su , Jun Wang , Yongchao Huang , Haitao Wang , Ning Liu , Jun Cheng , Yingbin Hu
IPC: H01L29/786 , G11C19/28 , H01L29/66
Abstract: A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.
-
9.发明授权公开(公告)号：US11335710B2
公开(公告)日：2022-05-17
申请号：US16936447
申请日：2020-07-23
Inventor： Qinghe Wang , Tongshang Su , Yongchao Huang , Yingbin Hu , Yang Zhang , Haitao Wang , Ning Liu , Guangyao Li , Zheng Wang , Yu Ji , Jinliang Hu , Wei Song , Jun Cheng , Liangchen Yan
Abstract: A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer.
-
公开(公告)号：US10559601B2
公开(公告)日：2020-02-11
申请号：US15580240
申请日：2017-06-23
Inventor： Tongshang Su , Jun Cheng , Ce Zhao , Bin Zhou , Dongfang Wang , Guangcai Yuan
IPC: H01L27/14 , H01L29/15 , H01L31/036 , H01L27/12 , G02F1/133 , G09G3/3283 , G09G3/3291 , H01L29/417 , H01L51/05 , H01L27/28 , H01L51/10 , H01L27/32
Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
-
-
-
-
-
-
-
-
-
Search Results
48
records
(took 0.023 seconds)
