公开(公告)号：US09264046B2

公开(公告)日：2016-02-16

申请号：US14626445

申请日：2015-02-19

Applicant: Broadcom Corporation

Inventor： David Chang ,  Ajat Hukkoo

IPC: H03K19/096 ,  G06F5/16 ,  G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F1/10 ,  H01F38/14 ,  H02J5/00

CPC classification number: H03K19/096 ,  G06F1/00 ,  G06F1/10 ,  G06F1/266 ,  G06F1/3287 ,  G06F5/16 ,  H01F38/14 ,  H02J50/05 ,  H02J50/10

Abstract: The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.

公开(公告)号：US09501089B2

公开(公告)日：2016-11-22

申请号：US14879905

申请日：2015-10-09

Applicant: Broadcom Corporation

Inventor： David Chang ,  Ajat Hukkoo

IPC: H01L23/02 ,  G06F1/10 ,  H03L7/06

CPC classification number: G06F1/10 ,  H03L7/06

Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

公开(公告)号：US09000805B2

公开(公告)日：2015-04-07

申请号：US13849115

申请日：2013-03-22

Applicant: Broadcom Corporation

Inventor： David Chang ,  Ajat Hukkoo

IPC: H03K19/096 ,  G06F5/16 ,  G06F1/26 ,  G06F1/32 ,  G06F1/00

CPC classification number: H03K19/096 ,  G06F1/00 ,  G06F1/10 ,  G06F1/266 ,  G06F1/3287 ,  G06F5/16 ,  H01F38/14 ,  H02J50/05 ,  H02J50/10

Abstract: The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.

Abstract translation: 本公开提供了一种用于在同步顺序逻辑电路内分配时钟信号的时钟分配网络。 时钟分配网络通过将时钟信号从主分配节点感应和/或电容耦合到同步顺序逻辑电路内的各个次分布节点来分配一个或多个时钟信号。 各个次级分布节点在相应的谐振频率处谐振，以产生响应于接收时钟信号而在同步顺序逻辑电路内使用的其它时钟信号。

公开(公告)号：US09172383B2

公开(公告)日：2015-10-27

申请号：US14027079

申请日：2013-09-13

Applicant: BROADCOM CORPORATION

Inventor： David Chang ,  Ajat Hukkoo

IPC: H01L23/02 ,  H03L7/06 ,  G06F1/10

CPC classification number: G06F1/10 ,  H03L7/06

Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Abstract translation: 公开了一种包括感应耦合时钟分配系统的集成电路封装。 本公开的示例性实施例包括耦合到主时钟线的传输模块，耦合到传输模块的时钟接收模块，时钟接收模块包括时钟输出线以及耦合到时钟的时钟输出线的电子电路 所述电子电路包括至少一个时钟元件，并且被配置为与通过时钟接收模块的时钟输出线接收的时钟信号同步地操作。 传输模块可以设置在IC封装的支撑壳上，并且电子电路和时钟接收模块可以设置在IC封装的半导体管芯上。