公开(公告)号：US08278905B2

公开(公告)日：2012-10-02

申请号：US12718840

申请日：2010-03-05

申请人： Barry Harvey ,  Steven Herbst

发明人： Barry Harvey ,  Steven Herbst

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： In accordance with an embodiment of the present invention, a bandgap voltage reference circuit includes a plurality of circuit branches, a plurality of resistors and a plurality of switches. The plurality of switches are used to selectively change over time which of the resistors are connected to be within a first one of the circuit branches and which of the resistors are connected to be within a second one of the circuit branches, to thereby reduce the effects that long term drift of the resistors have on a bandgap voltage output (VGO) of the bandgap voltage reference circuit.

摘要翻译： 根据本发明的实施例，带隙电压参考电路包括多个电路分支，多个电阻器和多个开关。 多个开关用于随时间选择性地改变电阻器中的哪一个被连接到电路分支的第一个中，并且电阻器中的哪一个连接到第二个电路分支中，从而减少效果 电阻器的长期漂移对带隙电压参考电路的带隙电压输出（VGO）有影响。

公开(公告)号：US20110127987A1

公开(公告)日：2011-06-02

申请号：US12717052

申请日：2010-03-03

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： In accordance with an embodiment of the present invention, a bandgap voltage reference circuit includes a group of X current sources, a plurality of circuit branches, and a plurality of switches. Each of the X current sources (where X≧3) produces a corresponding current that is substantially equal to the currents produced by the other current sources within the group. The plurality of circuit branches of the bandgap voltage reference circuit are collectively used to produce a bandgap voltage output (VGO). Each of the plurality of circuit branches receives at least one of the currents not received by the other circuit branches. The plurality of switches (e.g., controlled by a controller) selectively change over time which of the currents produced by the current sources are received by which of the plurality of circuit branches of the bandgap voltage reference circuit.

摘要翻译： 根据本发明的实施例，带隙电压参考电路包括一组X电流源，多个电路分支和多个开关。 X电流源（其中X≥3）中的每一个产生基本上等于由组内的其它电流源产生的电流的对应电流。 带隙电压参考电路的多个电路分支被共同用于产生带隙电压输出（VGO）。 多个电路分支中的每一个接收未被其它电路分支接收的电流中的至少一个。 多个开关（例如由控制器控制）选择性地随时间变化由电流源产生的电流中的哪一个由带隙电压参考电路的多个电路分支中的哪一个接收。

公开(公告)号：US07880459B2

公开(公告)日：2011-02-01

申请号：US12111796

申请日：2008-04-29

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/30

摘要： Provided herein are circuits and methods to generate a voltage proportional to absolute temperature (VPTAT) and/or a bandgap voltage output (VGO). A circuit includes a group of X transistors. A first subgroup of the X transistors are used to produce a first base-emitter voltage (VBE1). A second subgroup of the X transistors are used to produce a second base-emitter voltage (VBE2). The VPTAT can be produced by determining a difference between VBE1 and VBE2. Which of the X transistors are in the first subgroup and used to produce the first base-emitter voltage (VBE1), and/or which of the X transistors are in the second subgroup and used to produce the second base-emitter voltage (VBE2), change over time. Additionally, a circuit portion can be used to generates a voltage complimentary to absolute temperature (VCTAT) using at least one of the X transistors. The VPTAT and the VCTAT can be added to produce the VGO.

摘要翻译： 本文提供了产生与绝对温度（VPTAT）和/或带隙电压输出（VGO）成比例的电压的电路和方法。 电路包括一组X晶体管。 X晶体管的第一子组用于产生第一基极 - 发射极电压（VBE1）。 X晶体管的第二子组用于产生第二基极 - 发射极电压（VBE2）。 VPTAT可以通过确定VBE1和VBE2之间的差异来生成。 哪个X晶体管位于第一子组中并用于产生第一基极 - 发射极电压（VBE1），和/或X晶体管中的哪一个位于第二子组中并用于产生第二基极 - 发射极电压（VBE2） ， 随着时间的推移而变化。 此外，电路部分可以用于使用X晶体管中的至少一个来产生与绝对温度（VCTAT）互补的电压。 可以添加VPTAT和VCTAT以产生VGO。

公开(公告)号：US20090121698A1

公开(公告)日：2009-05-14

申请号：US11968551

申请日：2008-01-02

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： G05F1/10 ,  G05F3/16

CPC分类号： G05F3/30

摘要： A bandgap voltage reference circuit includes a first circuit portion and a second circuit portion. The first circuit portion generates a voltage complimentary to absolute temperature (VCTAT). The second circuit portion generates a voltage proportional to absolute temperature (VPTAT) that is added to the VCTAT to produce a bandgap voltage reference output. The first circuit portion includes a plurality of delta base-emitter voltage (VBE) generators, connected as a plurality of stacks of delta VBE generators. Each delta VBE generator can include a pair of transistors that operate at different current densities and thereby generate a difference in base-emitter voltages (ΔVBE). The plurality of delta VBE generators within each stack are connected to one another, and the plurality of stacks of delta VBE generators are connected to one another, such that the ΔVBEs generated by the plurality of delta VBE generators are arithmetically added to produce the VPTAT.

摘要翻译： 带隙电压参考电路包括第一电路部分和第二电路部分。 第一电路部分产生与绝对温度（VCTAT）互补的电压。 第二电路部分产生与绝对温度成比例的电压（VPTAT），其被加到VCTAT以产生带隙电压参考输出。 第一电路部分包括多个δ基极 - 发射极电压（VBE）发生器，其连接为多个VVA发生器的堆叠。 每个δBBE发生器可以包括在不同的电流密度下工作的一对晶体管，从而产生基极 - 发射极电压（DeltaVBE）的差异。 每个堆叠内的多个δBBE发生器彼此连接，并且ΔVBE发生器的多个堆叠彼此连接，使得由多个ΔBEE发生器产生的ΔVBE被算术地相加以产生VPTAT。

公开(公告)号：US07459978B2

公开(公告)日：2008-12-02

申请号：US11234010

申请日：2005-09-23

申请人： Robert David Zucker ,  Barry Harvey

发明人： Robert David Zucker ,  Barry Harvey

IPC分类号： H03F3/04

CPC分类号： H03F3/347 ,  H03F1/42 ,  H03F3/3432 ,  H03F3/50 ,  H03F3/505 ,  H03F2200/36

摘要： Ground skimming output stages that are designed to drive wideband signals with the ability to provide a high quality output signal all the way to the low supply rail are provided. In accordance with an embodiment of the present invention, the output stage of the present invention includes a translinear current controller, an output transistor and a current mirror. While not limited thereto, embodiments of the present invention only require a single positive power supply, consistent with the recent trend toward integrated circuits that only require a single low voltage power supply.

摘要翻译： 提供了设计用于驱动宽带信号的地面分选输出级，能够向低电源轨提供高质量的输出信号。 根据本发明的实施例，本发明的输出级包括一个跨线电流控制器，一个输出晶体管和一个电流镜。 尽管不限于此，本发明的实施例仅需要单个正电源，这与最近仅需要单个低电压电源的集成电路的趋势一致。

公开(公告)号：US06573943B1

公开(公告)日：2003-06-03

申请号：US09398375

申请日：1999-09-17

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： H04N508

CPC分类号： H04N5/08

摘要： A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output. Buffering is provided at the input of the negative peak detector by amplifier (600) to reduce any DC offset from the diode of the negative peak detector. To prevent amplifier DC offset error voltages from affecting the perceived VSLICE level, an amplifier (800) can be connected in a first position TTIP as part of a negative peak detector to store VTIP on a capacitor, in a second position TH as part of a sample and hold circuit to store VREF on a capacitor, and in a third position TCOMP to compare VSLICE+VTIP measured from the capacitors with the composite video signal to generate the overall circuit output.

摘要翻译： 用于产生视频同步定时信号的电路包括用于跟随复合视频信号（图1）的变化的负峰值检测器（图5），而不是钳制复合视频信号的最大负电压。 负峰值检测器提供表示复合视频信号的同步尖端处的电压的电压电平VTIP。 使用采样和保持电路（700,702,704）将偏移VSLICE添加到VTIP，VSLICE是复合视频信号的breezeway，彩色脉冲串或后沿段的电压电平，或这些段的组合 。 采样和保持电路产生信号VREF，并通过电阻分压器（708,710）连接到负峰值检测器，以形成提供给用作比较器的放大器（606）的信号VTIP + VSLICE。 在比较器（606）中将信号VSLICE + VTIP与复合视频信号进行比较，以提供总体电路输出。 通过放大器（600）在负峰值检测器的输入处提供缓冲以减少与负峰值检测器的二极管的任何DC偏移。 为了防止放大器DC偏移误差电压影响感知的VSLICE电平，放大器（800）可以连接在第一位置TTIP中，作为负峰值检测器的一部分，以将VTIP存储在电容器上，在第二位置TH中作为 采样和保持电路将VREF存储在电容器上，在第三个位置TCOMP将电容器测量的VSLICE + VTIP与复合视频信号进行比较，以产生总体电路输出。

公开(公告)号：US06501317B2

公开(公告)日：2002-12-31

申请号：US09828398

申请日：2001-04-06

申请人： Xijian Lin ,  Barry Harvey ,  Alexander Fairgrieve

发明人： Xijian Lin ,  Barry Harvey ,  Alexander Fairgrieve

IPC分类号： H03K522

CPC分类号： H03H11/265

摘要： A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current. A wide frequency tuning range of a ring oscillator using the delay circuit of FIG. 2 is provided because the operating frequency for a ring oscillator will be directly proportional to the tail current through transistor 101.

摘要翻译： 提供了一种用于锁相环（PLL）的环形振荡器的延迟电路。 延迟电路包括NMOS晶体管102和103的差分对，NMOS晶体管101为差分对提供尾电流。 互补NMOS和PMOS负载晶体管104,106和105,107为差分晶体管102和103提供负载。晶体管111-114和121-122与放大器130一起为延迟器提供偏置。 放大器130具有设置为VDD-VCLAMP的非反相输入。 根据配置，在延迟器件的输出VOUT +和VOUT-上提供从VDD到VDD-VCLAMP的恒定输出电压摆幅，与用于设置尾部电流的控制电压VCTL无关。 NMOS负载晶体管104与图3中的PMOS晶体管4相反。 1，不影响栅极寄生电容，能够在不消耗更多电源电流的情况下实现高运行速度。 使用图1的延迟电路的环形振荡器的宽频率调谐范围。 提供了图2，因为环形振荡器的工作频率将与通过晶体管101的尾流成正比。

公开(公告)号：US5589798A

公开(公告)日：1996-12-31

申请号：US444932

申请日：1995-05-19

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： H03F3/30 ,  H03F3/26 ,  H03F1/14

CPC分类号： H03F3/3066

摘要： A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C.sub.IN) on the negative, or inverting input terminal (V.sub.IN-). Additional circuitry in the input stage subtracts the matching current from the error current created by C.sub.IN to cancel the error current due to C.sub.IN and thus eliminate the peaking of gain at high frequencies caused by C.sub.IN. In addition to cancellation of C.sub.IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

公开(公告)号：US07528818B2

公开(公告)日：2009-05-05

申请号：US11237075

申请日：2005-09-28

申请人： Dong Zheng ,  Robert L. Lyle, Jr. ,  Barry Harvey ,  Brian B. North

发明人： Dong Zheng ,  Robert L. Lyle, Jr. ,  Barry Harvey ,  Brian B. North

IPC分类号： G09G3/36

CPC分类号： H05B41/3927 ,  G09G3/2014 ,  G09G3/3406 ,  H05B41/282

摘要： An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.

摘要翻译： 用于控制诸如根据脉宽调制（PWM）信号供电的冷阴极荧光灯的实用设备的操作的装置和方法包括模拟传感器，其监视该效用器件以导出输出信号代表 的PWM信号。 集成模数转换器（ADC），其耦合到传感器并且具有与PWM信号的周期的整数倍同步的操作，产生代表公用设备的输出的平均值的输出。

公开(公告)号：US20080278137A1

公开(公告)日：2008-11-13

申请号：US12111796

申请日：2008-04-29

申请人： Barry Harvey

发明人： Barry Harvey

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： Provided herein are circuits and methods to generate a voltage proportional to absolute temperature (VPTAT) and/or a bandgap voltage output (VGO). A circuit includes a group of X transistors. A first subgroup of the X transistors are used to produce a first base-emitter voltage (VBE1). A second subgroup of the X transistors are used to produce a second base-emitter voltage (VBE2). The VPTAT can be produced by determining a difference between VBE1 and VBE2. Which of the X transistors are in the first subgroup and used to produce the first base-emitter voltage (VBE1), and/or which of the X transistors are in the second subgroup and used to produce the second base-emitter voltage (VBE2), change over time. Additionally, a circuit portion can be used to generates a voltage complimentary to absolute temperature (VCTAT) using at least one of the X transistors. The VPTAT and the VCTAT can be added to produce the VGO.

摘要翻译： 本文提供了产生与绝对温度（VPTAT）和/或带隙电压输出（VGO）成比例的电压的电路和方法。 电路包括一组X晶体管。 X晶体管的第一子组用于产生第一基极 - 发射极电压（VBE 1）。 X晶体管的第二子组用于产生第二基极 - 发射极电压（VBE 2）。 VPTAT可以通过确定VBE 1和VBE 2之间的差异来生成。 哪个X晶体管位于第一子组中并用于产生第一基极 - 发射极电压（VBE1），和/或X晶体管中的哪一个位于第二子组中并用于产生第二基极 - 发射极电压（VBE 2），随着时间的推移而改变。 此外，电路部分可以用于使用X晶体管中的至少一个来产生与绝对温度（VCTAT）互补的电压。 可以添加VPTAT和VCTAT以产生VGO。