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1.发明授权Method and system for a multi-level virtual/real cache system with synonym resolution 有权具有同义词解析的多级虚拟/真实缓存系统的方法和系统公开(公告)号：US08041894B2
公开(公告)日：2011-10-18
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
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2.发明申请METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION 有权具有同步分辨率的多级虚拟/实时缓存系统的方法和系统公开(公告)号：US20090216949A1
公开(公告)日：2009-08-27
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
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3.发明授权Method, system, and computer program product for handling errors in a cache without processor core recovery 有权用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
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4.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY 有权方法，系统和计算机程序产品，用于处理高速缓存中的错误，无需处理器核心恢复公开(公告)号：US20090204766A1
公开(公告)日：2009-08-13
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
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5.发明授权公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。
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6.发明申请公开(公告)号：US20090210627A1
公开(公告)日：2009-08-20
申请号：US12031923
申请日：2008-02-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。
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公开(公告)号：US08627047B2
公开(公告)日：2014-01-07
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。
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8.发明申请MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权微处理器和方法，用于存储存储数据的存储数据在没有存储器模型限制的系统中的背景数据公开(公告)号：US20090210632A1
公开(公告)日：2009-08-20
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。
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9.发明授权Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法公开(公告)号：US08468306B2
公开(公告)日：2013-06-18
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。
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10.发明申请PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权在没有记忆模型限制的系统中存储数据转发的处理器和方法公开(公告)号：US20090210679A1
公开(公告)日：2009-08-20
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。
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