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1.发明授权Method, system, and computer program product for handling errors in a cache without processor core recovery 有权用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
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2.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY 有权方法，系统和计算机程序产品，用于处理高速缓存中的错误，无需处理器核心恢复公开(公告)号：US20090204766A1
公开(公告)日：2009-08-13
申请号：US12029516
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译： 用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。 将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。 在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别 缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。 执行流水线从较高级别的存储位置访问所请求的数据的副本。
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3.发明申请METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION 有权具有同步分辨率的多级虚拟/实时缓存系统的方法和系统公开(公告)号：US20090216949A1
公开(公告)日：2009-08-27
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
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4.发明授权Method and system for a multi-level virtual/real cache system with synonym resolution 有权具有同义词解析的多级虚拟/真实缓存系统的方法和系统公开(公告)号：US08041894B2
公开(公告)日：2011-10-18
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译： 具有同义词解析的多级虚拟/真实缓存系统的方法和系统。 一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合 在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。
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5.发明授权公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。
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6.发明申请公开(公告)号：US20090210627A1
公开(公告)日：2009-08-20
申请号：US12031923
申请日：2008-02-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。
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公开(公告)号：US09164761B2
公开(公告)日：2015-10-20
申请号：US12033351
申请日：2008-02-19
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/3879
摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.
摘要翻译： 流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。 处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。 处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。 该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。 特殊指令的执行在相应的单位启动。 如果执行特殊指令的单元不是LSU，则将数据发送到LSU。 作为执行特殊指令的结果，从LSU接收数据。 数据被提供给请求者。
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公开(公告)号：US08627047B2
公开(公告)日：2014-01-07
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。
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9.发明授权Method, system and computer program product for storing external device result data 失效用于存储外部设备结果数据的方法，系统和计算机程序产品公开(公告)号：US08250336B2
公开(公告)日：2012-08-21
申请号：US12036695
申请日：2008-02-25
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3879
摘要： A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.
摘要翻译： 一种用于从外部设备存储结果数据的方法，系统和计算机程序产品。 该方法包括从外部设备接收结果数据，在系统接收。 结果数据存储到存储数据缓冲区中。 存储数据缓冲器被系统用于包含通常由系统生成的存储数据。 执行特殊存储指令以将结果数据存储到系统中的存储器中。 特殊商店指令包括商店地址。 所述执行包括基于所提供的指示信息执行所述存储地址的地址计算，以及利用所述系统利用的用于存储由所述系统正常生成的数据的数据路径来更新所述存储数据缓冲器的存储位置。
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10.发明申请PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT INCLUDING SPECIALIZED STORE QUEUE AND BUFFER DESIGN FOR SILENT STORE IMPLEMENTATION 有权处理器，方法和计算机程序产品，其中包括专门针对存储商店的特殊店铺和缓冲设计，公开(公告)号：US20090210655A1
公开(公告)日：2009-08-20
申请号：US12031998
申请日：2008-02-15
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826
摘要： A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data buffer; compare logic for receiving old data from the old data buffer and new data from the new data buffer and comparing if the old data matches the new data, and if there is a match determining an existence of a silent store; and store data control logic for limiting store operations while the silent store exists. A method and a computer program product are provided.
摘要翻译： 包括用于限制存储操作的架构的处理器包括：作为数据合并逻辑的输入的数据输入和高速缓存输入; 用于向旧数据缓冲器提供输出的合并缓冲器，保持存储器位置的副本和与新数据缓冲器的双向通信; 比较用于从旧数据缓冲器接收旧数据和来自新数据缓冲器的新数据的比较逻辑，并比较旧数据是否与新数据匹配，以及是否存在确定静默存储的存在的匹配; 并存储用于限制存储操作的数据控制逻辑，同时存在无声存储。 提供了一种方法和计算机程序产品。
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