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    Method and system for handling cache coherency for self-modifying code
    1.
    发明授权
    Method and system for handling cache coherency for self-modifying code 有权
    用于处理缓存一致性的自修改代码的方法和系统

    公开(公告)号：US08015362B2

    公开(公告)日：2011-09-06

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE
    2.
    发明申请
    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE 有权
    用于处理自我修改代码的高速缓存的方法和系统

    公开(公告)号：US20090210627A1

    公开(公告)日：2009-08-20

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION
    3.
    发明申请
    METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION 有权
    串行翻译查询缓冲区访问方法地址转换参数修改方法

    公开(公告)号：US20090210650A1

    公开(公告)日：2009-08-20

    申请号：US12032178

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Lisa C. Heller ,  Chung-Lung Kevin Shum

    发明人： Gregory W. Alexander ,  Lisa C. Heller ,  Chung-Lung Kevin Shum

    IPC分类号： G06F12/02

    CPC分类号： G06F12/1027 ,  G06F2212/684

    摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.

    摘要翻译： 本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。 提供处理器和计算机程序产品。

    Serializing translation lookaside buffer access around address translation parameter modification
    4.
    发明授权
    Serializing translation lookaside buffer access around address translation parameter modification 有权
    序列化翻译后备缓冲区访问围绕地址转换参数修改

    公开(公告)号：US08433855B2

    公开(公告)日：2013-04-30

    申请号：US12032178

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Lisa C. Heller ,  Chung-Lung Kevin Shum

    发明人： Gregory W. Alexander ,  Lisa C. Heller ,  Chung-Lung Kevin Shum

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F2212/684

    摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.

    摘要翻译： 本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。 提供处理器和计算机程序产品。

    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA
    5.
    发明申请
    COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA 失效
    收集计算机处理器仪表数据

    公开(公告)号：US20110154298A1

    公开(公告)日：2011-06-23

    申请号：US12645687

    申请日：2009-12-23

    申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    IPC分类号： G06F9/44

    CPC分类号： G06F11/348 ,  G06F11/3409

    摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

    摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

    Collecting computer processor instrumentation data
    7.
    发明授权
    Collecting computer processor instrumentation data 失效
    收集计算机处理器仪表数据

    公开(公告)号：US08453124B2

    公开(公告)日：2013-05-28

    申请号：US12645687

    申请日：2009-12-23

    申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

    IPC分类号： G06F9/44

    CPC分类号： G06F11/348 ,  G06F11/3409

    摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

    摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。