公开(公告)号：US20060236074A1

公开(公告)日：2006-10-19

申请号：US11105593

申请日：2005-04-14

申请人： Barry Williamson ,  Gerard Williams ,  David Williamson

发明人： Barry Williamson ,  Gerard Williams ,  David Williamson

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054

摘要： A data processor operable to process data said data processor being operable to perform a plurality of processes or a plurality of applications on said data, said data processor comprising: a cache; a data storage unit operable to store a process or application identifier defining a process or application that is currently executing on said data processor on said data; wherein a data item storage location within said cache is indicated by an address, and said data processor further comprises: a hash value generator operable to generate a hash value from at least some of said bits of said address and at least some bits of said process or application identifier, said hash value having fewer bits than said address.

摘要翻译： 一种数据处理器，可操作用于处理数据，所述数据处理器可操作以在所述数据上执行多个处理或多个应用，所述数据处理器包括：高速缓存; 数据存储单元，用于存储定义当前在所述数据处理器上对所述数据执行的处理或应用程序的过程或应用程序标识符; 其中所述高速缓存内的数据项存储位置由地址指示，并且所述数据处理器还包括：哈希值生成器，用于从所述地址的所述位的至少一些位和所述处理的至少某些位生成哈希值 或应用标识符，所述散列值具有比所述地址少的位。

公开(公告)号：US20070028051A1

公开(公告)日：2007-02-01

申请号：US11193633

申请日：2005-08-01

申请人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda ,  Raul Garibay

发明人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda ,  Raul Garibay

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  G06F2212/1028 ,  Y02D10/13

摘要： The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

摘要翻译： 该应用公开了一种可操作以处理数据的数据处理器，所述数据处理器包括：具有由地址识别的数据项存储位置的高速缓存; 哈希值生成器，用于从所述地址的所述比特中的至少一些产生哈希值，所述哈希值具有比所述地址少的比特; 缓冲器，用于存储与所述高速缓存中的多个存储位置相关的多个散列值; 其中响应于访问所述数据项存储位置的请求，所述数据处理器可操作以将从所述地址生成的散列值与存储在所述缓冲器内的所述多个散列值中的至少一些进行比较。 该比较提供数据项的存储位置的指示。

公开(公告)号：US20070028047A1

公开(公告)日：2007-02-01

申请号：US11193634

申请日：2005-08-01

申请人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda

发明人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  Y02D10/13

摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.

摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。

公开(公告)号：US20100161901A9

公开(公告)日：2010-06-24

申请号：US11193634

申请日：2005-08-01

申请人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda

发明人： Barry Williamson ,  Gerard Williams ,  Muralidharan Chinnakonda

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  Y02D10/13

摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.

摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。

公开(公告)号：US20050017763A1

公开(公告)日：2005-01-27

申请号：US10626871

申请日：2003-07-25

申请人： Richard Slobodnik ,  Gerard Williams ,  Mark Silla

发明人： Richard Slobodnik ,  Gerard Williams ,  Mark Silla

IPC分类号： G06F1/08 ,  H03K3/00

CPC分类号： G06F1/08

摘要： A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.

摘要翻译： 公开了一种处理器时钟控制装置，其可操作以控制以无毛刺方式输入到处理器的时钟信号之间的切换。 处理器时钟控制装置包括：至少两个时钟信号输入，每个可操作以接收时钟信号，所述时钟信号包括第一和第二时钟信号; 传感器，其可操作以感测所述第一和所述第二时钟信号; 时钟信号输出，其可操作以输出用于输入到处理器的时钟信号; 以及时钟切换信号输入，用于接收可操作以控制从所述第一时钟信号输出到所述第二时钟信号的所述时钟信号的切换的切换信号; 其中所述处理器时钟控制装置在接收到所述时钟切换信号以操作所述第一时钟信号时可操作，并且当所述第一时钟信号从第一预定电平转变到第二电平时，所述处理器时钟控制装置可操作以保持所述时钟信号 在所述第二电平输出，然后感测所述第二时钟信号，并且当所述第二时钟信号从所述第二电平转换到所述第一预定电平时，输出所述第二时钟信号。

公开(公告)号：US20050223130A1

公开(公告)日：2005-10-06

申请号：US10815982

申请日：2004-04-02

申请人： Tan Tran ,  Richard Grisenthwaite ,  Gerard Williams

发明人： Tan Tran ,  Richard Grisenthwaite ,  Gerard Williams

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 operable to perform further data processing operations in response to receipt of said processor clock signal CLK. The two portions of the core being operable to be independently enabled such that one portion may be active while the other is inactive.

摘要翻译： 数据处理器核心10，其包括存储器访问接口部分30，其可操作以在外部数据源与至少一个与所述数据处理器核心相关联的存储器之间执行数据传输操作;以及数据处理部分12，可操作以执行另外的数据处理操作 接收所述处理器时钟信号CLK。 核心的两个部分可操作以独立地启用，使得一个部分可以是活动的，而另一个部分是不活动的。

公开(公告)号：US20050223129A1

公开(公告)日：2005-10-06

申请号：US10815961

申请日：2004-04-02

申请人： Tan Tran ,  Gerard Williams ,  David Matheny ,  David Flynn

发明人： Tan Tran ,  Gerard Williams ,  David Matheny ,  David Flynn

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  G06F13/36

CPC分类号： G06F13/1657 ,  G06F13/28

摘要： A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

摘要翻译： 一种数据处理器核心10，包括：存储器访问接口部分30，可操作以在外部数据源与与所述数据处理器核心相关联的至少一个存储器120之间执行数据传送操作; 数据处理部分12，用于执行数据处理操作; 读/写端口40，其可操作以将数据从所述处理器核传输到至少两个总线75A，75B，所述至少两个总线可操作以在所述处理器核心10和所述至少一个存储器120之间提供数据通信， 至少一个存储器120包括至少两个部分120A，120B，所述至少两个总线75A，75B中的每一个可操作以提供对所述至少两个部分120A，120B中的相应部分的数据访问; 与所述读/写端口40相关联的仲裁逻辑110; 其中所述仲裁逻辑可操作用于将请求数据访问的数据访问请求路由到从所述存储器访问接口接收的所述至少一个存储器的一部分中的数据访问到所述至少两个总线之一，提供对所述至少一个的所述一个部分的访问 存储器，并且路由进一步的数据访问请求，请求从所述数据处理部分接收的所述至少一个存储器的另一部分中的数据访问到所述至少两个总线中的另一个，提供对所述至少一个 存储器，所述数据访问请求的路由在相同的时钟周期期间执行。