公开(公告)号：US20060215440A1

公开(公告)日：2006-09-28

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07397681B2

公开(公告)日：2008-07-08

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C27/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07012834B2

公开(公告)日：2006-03-14

申请号：US10829807

申请日：2004-04-22

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

公开(公告)号：US07688621B2

公开(公告)日：2010-03-30

申请号：US11949299

申请日：2007-12-03

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

摘要翻译： 一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

公开(公告)号：US07548451B2

公开(公告)日：2009-06-16

申请号：US11896721

申请日：2007-09-05

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。

公开(公告)号：US20080055972A1

公开(公告)日：2008-03-06

申请号：US11896721

申请日：2007-09-05

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。

公开(公告)号：US07304886B2

公开(公告)日：2007-12-04

申请号：US11324907

申请日：2006-01-04

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

摘要翻译： 具有脉冲选择电路，电流控制电路和电流驱动电路的相变存储器阵列的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

公开(公告)号：US07242605B2

公开(公告)日：2007-07-10

申请号：US10937943

申请日：2004-09-11

申请人： Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

摘要翻译： 提供了一种相变存储器件和方法，其将相变材料的电阻保持在恒定电阻范围内的复位状态。 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。

公开(公告)号：US20060109720A1

公开(公告)日：2006-05-25

申请号：US11324907

申请日：2006-01-04

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

摘要翻译： 具有脉冲选择电路，电流控制电路和电流驱动电路的相变存储器阵列的写入驱动电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

公开(公告)号：US07817465B2

公开(公告)日：2010-10-19

申请号：US12453420

申请日：2009-05-11

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： A phase change random access (PRAM) memory may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

摘要翻译： 相位随机存取（PRAM）存储器可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，该补偿单元被配置为向感测节点提供补偿 电流以补偿由流过多个相变存储器单元之一的电流引起的感测节点的电平的降低，以及被配置为将感测节点的电平与参考电平进行比较并输出结果的读出放大器 的比较。