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公开(公告)号：US11342925B2
公开(公告)日：2022-05-24
申请号：US17296672
申请日：2020-08-13
发明人： Xiangye Wei , Liming Xiu
摘要： A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part and the second fractional part are not equal, and a period of the first output signal and a period of the second output signal are not equal.
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公开(公告)号：US11949422B2
公开(公告)日：2024-04-02
申请号：US17642023
申请日：2021-03-09
发明人： Xiangye Wei , Liming Xiu
摘要： A pulse width modulation (PWM) circuit, a method for PWM, and an electronic device are provided. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit, wherein a ratio of the first target frequency control word to the second target frequency control word is the target duty cycle; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words.
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公开(公告)号：US11916557B2
公开(公告)日：2024-02-27
申请号：US17836419
申请日：2022-06-09
发明人： Xiangye Wei , Liming Xiu , Yuhai Ma
IPC分类号： H03K5/1252 , G06F1/04 , H03K5/00
CPC分类号： H03K5/1252 , G06F1/04 , H03K5/00006
摘要： A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit (10) includes a control circuit (11) and a signal generation circuit (12). The control circuit (11) is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit (12) is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.
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公开(公告)号：US11868511B2
公开(公告)日：2024-01-09
申请号：US17794142
申请日：2021-08-05
发明人： Xiangye Wei , Yiming Bai , Liming Xiu
摘要： Provided is a digital fingerprint generator. The digital fingerprint generator includes: a control circuit, configured to generate a control word; a first pulse generation circuit, connected to the control circuit, and configured to output a first pulse signal in response to the control word; a second pulse generation circuit, connected to the control circuit, having a same structure as the first pulse generation circuit, and configured to output a second pulse signal in response to the control word; and an output circuit, connected to the first pulse generation circuit and the second pulse generation circuit, and configured to output a digital fingerprint based on the first pulse signal and the second pulse signal according to a predetermined first rule.
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5.发明公开公开(公告)号：US20230409074A1
公开(公告)日：2023-12-21
申请号：US18459053
申请日：2023-08-31
发明人： Xiangye Wei , Liming Xiu
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A method for generating spread-spectrum synchronous clock signals includes comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback; generating a first control signal and a second control signal; determining an integer part I of a control word F to track the first frequency; registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0
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公开(公告)号：US11799578B2
公开(公告)日：2023-10-24
申请号：US17413367
申请日：2020-01-19
发明人： Xiangye Wei , Liming Xiu , Yiming Bai
CPC分类号： H04J3/0658 , H03L7/18 , H04J3/0641 , H04J3/0679
摘要： This is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.
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7.发明授权公开(公告)号：US11689193B2
公开(公告)日：2023-06-27
申请号：US17765933
申请日：2021-03-09
发明人： Xiangye Wei , Liming Xiu
摘要： A clock signal generation circuit, a method for generating a clock signal, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit can generate an initial clock signal having an initial frequency; a control word providing circuit can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.
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公开(公告)号：US20230123009A1
公开(公告)日：2023-04-20
申请号：US16975258
申请日：2019-10-09
发明人： Xiangye Wei , Liming Xiu
IPC分类号： H03L7/089 , H03L7/099 , H03K19/173
摘要： The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.
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9.发明授权公开(公告)号：US11196454B2
公开(公告)日：2021-12-07
申请号：US16975261
申请日：2019-10-09
发明人： Xiangye Wei , Liming Xiu , Yuhai Ma , Xin Li
摘要： A digital transceiver is provided. The digital transceiver includes a clock generator configured to generate a first clock signal having a first frequency of a fixed value and a transmitter driven by the first clock signal of the first frequency to transmit data. Additionally, the digital transceiver includes an inverter coupled to the clock generator to generate an inverted first clock signal of the first frequency. Further, it includes a frequency detector configured to compare the first frequency with a second frequency of a feedback signal in a loop of feedback to determine a frequency control word F. Furthermore, it includes a digitally-controlled oscillator driven by the frequency control word F in the loop of feedback to output a second clock signal with a time-average frequency substantially synchronous to the first frequency with a boundary spread and a receiver driven by the second clock signal to receive the data.
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公开(公告)号：US11031926B2
公开(公告)日：2021-06-08
申请号：US16975267
申请日：2019-10-21
发明人： Xiangye Wei , Liming Xiu , Yiming Bai , Xin Li
摘要： A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.
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