公开(公告)号：US08612659B1

公开(公告)日：2013-12-17

申请号：US12967979

申请日：2010-12-14

申请人： Benjamin C. Serebrin ,  Raviprasad Mummidi

发明人： Benjamin C. Serebrin ,  Raviprasad Mummidi

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812 ,  G06F9/5027 ,  G06F2209/5021

摘要： Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.

摘要翻译： 基于分配给由处理器执行的代码的优先级值，硬件中断被路由到虚拟化计算机系统的多个处理器之一。 每个处理器动态地更新与其执行的代码相关联的优先级值，并且当产生硬件中断时，硬件中断被路由到正在执行具有最低优先级值的代码来处理硬件中断的处理器。 因此，中断的路由可以偏离执行高优先级任务的处理器，或者上下文切换可能在计算上是昂贵的。

公开(公告)号：US08799628B2

公开(公告)日：2014-08-05

申请号：US12551240

申请日：2009-08-31

申请人： David A. Kaplan ,  Daniel B. Hopper ,  Benjamin C. Serebrin

发明人： David A. Kaplan ,  Daniel B. Hopper ,  Benjamin C. Serebrin

IPC分类号： G06F9/30

CPC分类号： G06F9/30058 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3844 ,  G06F9/3885

摘要： A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. Subsequent to the first command issuing, a second command is issued and executed. Execution of the second command includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, a third command is issued and executed. Execution of the third command includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

摘要翻译： 公开了用于分支确定的方法和装置。 该方法包括在计算机处理器内发出的第一命令。 由计算机处理器执行第一命令包括评估一个或多个条件以设置一个或多个标志。 在第一个命令发出之后，发出并执行第二个命令。 执行第二命令包括使计算机处理器等待直到设置了一个或多个标志。 在发出第一和第二命令之后，发出并执行第三命令。 执行第三命令包括基于由第一命令设置的一个或多个标志中的至少一个的值执行跳转操作。

公开(公告)号：US08561060B2

公开(公告)日：2013-10-15

申请号：US11740463

申请日：2007-04-26

申请人： Benjamin C. Serebrin ,  Michael J. Haertel

发明人： Benjamin C. Serebrin ,  Michael J. Haertel

IPC分类号： G06F9/455

CPC分类号： G06F9/45558 ,  G06F2009/45579

摘要： In one embodiment, a processor comprises one or more registers coupled to an execution core. The registers are configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution. Additionally, the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event. The execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event.

摘要翻译： 在一个实施例中，处理器包括耦合到执行核心的一个或多个寄存器。 寄存器被配置为存储拦截配置，该拦截配置识别在访客执行期间多个拦截事件中的哪一个被拦截。 此外，截取配置针对每个启用的截取事件识别为响应于启用的截取事件的检测而使用至少两个退出机制中的哪一个。 执行核心被配置为在执行访客期间检测启用的拦截事件之一，并且使用针对该检测到的拦截事件的拦截配置中标识的退出机制退出客人。

公开(公告)号：US08234429B2

公开(公告)日：2012-07-31

申请号：US12613076

申请日：2009-11-05

申请人： Benjamin C. Serebrin

发明人： Benjamin C. Serebrin

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

摘要： In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example.

摘要翻译： 在一个实施例中，提供了中断接受控制电路。 中断接受控制电路可以响应于在客户端中发出的IPI（或设备中断）来监视系统中的一个或多个客户中断控制器，以确定客人中的每个目标vCPU是否已经接受了中断。 如果不是，则在一个实施例中，中断接受控制电路可以将缺乏接受传达给VMM。 例如，VMM可能会尝试安排不接受中断的vCPU。

公开(公告)号：US20110197003A1

公开(公告)日：2011-08-11

申请号：US12961186

申请日：2010-12-06

申请人： Benjamin C. Serebrin ,  Rodney W. Schmidt ,  David A. Kaplan ,  Mark D. Hummel

发明人： Benjamin C. Serebrin ,  Rodney W. Schmidt ,  David A. Kaplan ,  Mark D. Hummel

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579

摘要： In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

摘要翻译： 在一个实施例中，设备中断管理器可以被配置为从分配给访客的设备接收中断。 设备中断管理器可以被配置为发送针对系统存储器中的存储器位置的操作以记录客户机内的虚拟处理器的中断，其中中断将被传递到目标虚拟处理器。 在一个实施例中，虚拟机管理器可以被配置为检测设备中断管理器对于当前未执行的虚拟处理器已经记录了中断。 虚拟机管理器可以被配置为调度虚拟处理器以在硬件处理器上执行，或者可以响应于该中断来优先处理虚拟处理器以进行调度。

公开(公告)号：US20110010707A1

公开(公告)日：2011-01-13

申请号：US12498784

申请日：2009-07-07

申请人： Benjamin C. Serebrin ,  Michael Haertel

发明人： Benjamin C. Serebrin ,  Michael Haertel

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： A data processing device includes one or more state registers to store state information associated with an execution core of the device. Each state register includes an associated “dirty” bit. When a guest program is executed at the execution core, a dirty bit is set in response to a change in the state information at the associated state register. In response to a world switch from the guest program to a VMM, the state information at each state register is stored to memory only if the associated dirty bit is set. In addition, if the VMM changes any stored state information, it clears a “clean” bit associated with the changed information. In response to a world switch from the VMM to a guest, the state information associated with cleared clean bits is retrieved from memory.

摘要翻译： 数据处理装置包括一个或多个状态寄存器，用于存储与该装置的执行核心相关联的状态信息。 每个状态寄存器包括相关的“脏”位。 当在执行核心执行访客程序时，响应于关联状态寄存器中的状态信息的改变而设置脏位。 响应于从访客程序到VMM的世界切换，每个状态寄存器中的状态信息只有在相关的脏位被设置时才被存储到存储器中。 此外，如果VMM更改任何存储的状态信息，它将清除与更改的信息相关联的“干净”位。 响应于从VMM到访客的世界切换，从存储器检索与清除的清除位相关联的状态信息。

公开(公告)号：US20100191887A1

公开(公告)日：2010-07-29

申请号：US12613076

申请日：2009-11-05

申请人： Benjamin C. Serebrin

发明人： Benjamin C. Serebrin

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

摘要： In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example.

摘要翻译： 在一个实施例中，提供了中断接受控制电路。 中断接受控制电路可以响应于在客户端中发出的IPI（或设备中断）来监视系统中的一个或多个客户中断控制器，以确定客人中的每个目标vCPU是否已经接受了中断。 如果不是，则在一个实施例中，中断接受控制电路可以将缺乏接受传达给VMM。 例如，VMM可能会尝试安排不接受中断的vCPU。

公开(公告)号：US20090222683A1

公开(公告)日：2009-09-03

申请号：US12039140

申请日：2008-02-28

申请人： Benjamin C. Serebrin ,  Robert M. Kallal

发明人： Benjamin C. Serebrin ,  Robert M. Kallal

IPC分类号： G06F1/00

CPC分类号： G06F1/14

摘要： In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.

摘要翻译： 在一个实施例中，一种装置包括一个或多个处理器和耦合到处理器的控制器。 每个处理器包括至少一个处理器时间戳计数器（TSC）和被配置为维持处理器TSC的第一控制单元。 控制器包括至少一个控制器TSC和被配置为维持控制器TSC的第二控制单元。 控制器被配置为响应于确定处理器TSC与控制器TSC不同步而发信号通知处理器。 响应于已经发信号通知处理器TSC不同步，处理器被配置为在为读取TSC指令生成结果之前将处理器TSC重新同步到控制器TSC。 响应于没有发信号通知处理器TSC不同步，处理器被配置为响应于处理器TSC生成结果而不重新同步。

公开(公告)号：US20090187729A1

公开(公告)日：2009-07-23

申请号：US12272956

申请日：2008-11-18

申请人： Benjamin C. Serebrin ,  Michael J. Haertel

发明人： Benjamin C. Serebrin ,  Michael J. Haertel

IPC分类号： G06F12/10

CPC分类号： G06F9/455 ,  G06F9/45537

摘要： In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

摘要翻译： 在一个实施例中，处理器在执行非客户代码期间支持备用地址空间（例如小型存储器或虚拟机监视器（VMM））。 备用地址空间可能是访客地址空间。 小型主机/ VMM中的指令可以指定数据访问的备用地址空间，允许小型存储器/ VMM通过备用地址空间读取访客存储器状态。 在另一个实施例中，处理器可以实现专用于小型存储器使用的页表基地址寄存器。 在另一个实施例中，小型存储器可以被实现为VMM地址空间中的指定入口点。

公开(公告)号：US09152570B2

公开(公告)日：2015-10-06

申请号：US13406144

申请日：2012-02-27

申请人： Bhavesh Mehta ,  Benjamin C. Serebrin

发明人： Bhavesh Mehta ,  Benjamin C. Serebrin

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/151 ,  G06F2212/651

摘要： In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, sub-pages can be virtually addressed at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, sub-pages can be virtually addressed at a granularity that is 1/(2M)-th of a memory page. The granularity of page sizes can be selected according to particular use cases. In the case of COW optimization, page sizes can be set statically between 4 KB and 2 MB or configured dynamically among multiple page sizes.

摘要翻译： 在具有虚拟机的计算机系统中，分配来宾虚拟地址范围的一个或多个未使用的位以进行混叠，使得可以将多个虚拟寻址的子页面映射到公共存储器页面。 当一个位被分配用于混叠时，子页面可以以存储器页面的一半的粒度来虚拟地寻址。 当M位被分配用于混叠时，子页面可以以存储器页面的1 /（2M）的粒度来虚拟地寻址。 可以根据具体的用例选择页面大小的粒度。 在COW优化的情况下，可以在4 KB到2 MB之间静态设置页面大小，或者在多个页面大小之间动态配置页面大小。