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公开(公告)号：US20100192029A1
公开(公告)日：2010-07-29
申请号：US12361814
申请日：2009-01-29
IPC分类号： G06F11/22
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译： 根据本公开的某些实施例，提供了一种信息处理系统。 信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。 控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收到的本地SMI信号基于全局SMI触发规则触发全局SMI，导致 所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。
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2.发明申请System and method for managing system management interrupts in a multiprocessor computer system 审中-公开用于管理多处理器计算机系统中的系统管理中断的系统和方法公开(公告)号：US20080082710A1
公开(公告)日：2008-04-03
申请号：US11540804
申请日：2006-09-29
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： A system and method is disclosed in which, during the execution of an interrupt handling sequence in one of the processor of a multiprocessor system, a processors write a reason code to a status register to identify the cause of the interrupt. The BIOS code of the system writes to an interrupt initiation register to cause each of the processors to enter an interrupt handling sequence. Each of the processors of the system handling the interrupt on the basis of the content of the status register, resulting in each of the processors synchronously handling an interrupt for an event that would otherwise result in a local interrupt.
摘要翻译： 公开了一种系统和方法，其中在多处理器系统的处理器之一执行中断处理序列期间，处理器将原因代码写入状态寄存器以识别中断的原因。 系统的BIOS代码写入中断启动寄存器，使每个处理器进入中断处理程序。 基于状态寄存器的内容处理中断的系统的每个处理器，导致每个处理器同步处理否则将导致本地中断的事件的中断。
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3.发明申请System and method for managing system management interrupts in a multiprocessor computer system 有权用于管理多处理器计算机系统中的系统管理中断的系统和方法公开(公告)号：US20080082711A1
公开(公告)日：2008-04-03
申请号：US11540805
申请日：2006-09-29
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译： 公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。 本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。 主处理器将识别系统管理中断的启动。 主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。 在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。 如果是这样，系统管理中断由本地处理器处理。 在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。
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公开(公告)号：US08122176B2
公开(公告)日：2012-02-21
申请号：US12361814
申请日：2009-01-29
IPC分类号： G06F13/24
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译： 根据本公开的某些实施例，提供了一种信息处理系统。 信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。 控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收的本地SMI信号基于全局SMI触发规则触发全局SMI，导致 所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。
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5.发明授权System and method for managing system management interrupts in a multiprocessor computer system 有权用于管理多处理器计算机系统中的系统管理中断的系统和方法公开(公告)号：US07721034B2
公开(公告)日：2010-05-18
申请号：US11540805
申请日：2006-09-29
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译： 公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。 本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。 主处理器将识别系统管理中断的启动。 主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。 在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。 如果是这样，系统管理中断由本地处理器处理。 在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。
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公开(公告)号：US20100023737A1
公开(公告)日：2010-01-28
申请号：US12178887
申请日：2008-07-24
IPC分类号： G06F15/177
CPC分类号： G06F11/2284
摘要： A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed by determining whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores.
摘要翻译： 测试模式初始化系统包括开始开机自检（POST），其中POST可以通过确定被测系统是否处于快速测试模式，并且响应于处于快速测试模式，仅初始化 被测系统中的所有存储器的一部分，并且仅初始化多个中央处理器单元（CPU）核心的一部分。
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7.发明申请System and Method for Providing Instant Video in an Information Handling System 有权在信息处理系统中提供即时视频的系统和方法公开(公告)号：US20120117302A1
公开(公告)日：2012-05-10
申请号：US12941544
申请日：2010-11-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/4401 , G06F9/4411
摘要： Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
摘要翻译： 在初始化信息处理系统的存储器之前，一种方法包括将用于图形接口设备的视频选项ROM代码的图像加载到与信息处理系统的处理器相关联的高速缓存器，以及执行视频选项ROM代码以初始化 图形界面设备。 该方法还包括执行存储器参考代码以初始化存储器，以及在执行存储器参考代码时，从图形接口设备提供状态信息。
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8.发明授权公开(公告)号：US07921266B2
公开(公告)日：2011-04-05
申请号：US12021755
申请日：2008-01-29
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor.
摘要翻译： 公开了一种在信息处理系统内访问存储器的系统和方法。 在一种形式中，访问存储器的方法可以包括检测第一处理器可访问的第一存储器访问节点的第一操作值，以及启动第一存储器访问节点的操作为第一数据速率值。 该方法还可以包括启动第二存储器访问节点到第二数据速率值的操作。 在一种形式中，第二数据速率值可以不同于第一数据速率值。 该方法还可以包括通过由处理器启用的操作系统来启用第一应用程序访问第一存储器访问节点或第二存储器访问节点。
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9.发明授权System and method for providing instant video in an information handling system 有权用于在信息处理系统中提供即时视频的系统和方法公开(公告)号：US08847967B2
公开(公告)日：2014-09-30
申请号：US12941544
申请日：2010-11-08
CPC分类号： G06F12/0862 , G06F9/4401 , G06F9/4411
摘要： Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
摘要翻译： 在初始化信息处理系统的存储器之前，一种方法包括将用于图形接口设备的视频选项ROM代码的图像加载到与信息处理系统的处理器相关联的高速缓存器，以及执行视频选项ROM代码以初始化 图形界面设备。 该方法还包括执行存储器参考代码以初始化存储器，以及在执行存储器参考代码时，从图形接口设备提供状态信息。
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公开(公告)号：US08078858B2
公开(公告)日：2011-12-13
申请号：US12178887
申请日：2008-07-24
IPC分类号： G06F15/177
CPC分类号： G06F11/2284
摘要： A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed to determine whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores.
摘要翻译： 测试模式初始化系统包括开始开机自检（POST），其中可以执行POST以确定被测系统是否处于快速测试模式，并且响应于处于快速测试模式，仅初始化 被测系统中的所有存储器的一部分，并且仅初始化多个中央处理器单元（CPU）核心的一部分。
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