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    Memory system including a memory device having a controlled output driver characteristic
    4.
    发明授权
    Memory system including a memory device having a controlled output driver characteristic 失效
    存储器系统，包括具有受控输出驱动器特性的存储器件

    公开(公告)号：US06608507B2

    公开(公告)日：2003-08-19

    申请号：US10230931

    申请日：2002-08-29

    申请人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

    发明人： Billy Wayne Garrett, Jr. ,  John B. Dillon ,  Michael Tak-Kei Ching ,  William F. Stonecypher ,  Andy Peng-Pui Chan ,  Matthew M. Griffin

    IPC分类号： H03B100

    CPC分类号： G11C7/1057 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/0298

    摘要： A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode. During the normal read operation, the first output driver is operable to output data onto the first signal line in accordance with the calibrated voltage swing level.

    摘要翻译： 一种存储系统和调整包含在存储器系统中的存储器件的输出驱动器特性的方法。 该方法包括向存储器件提供指定校准模式的命令，并且在校准模式期间，使用第一输出驱动器将电压电平驱动到第一信号线上。 第一电压电平是从驱动第一信号线上的电压电平的第一输出驱动器产生的电压摆幅的量导出的。 该方法还包括：主动地将第一比较器耦合到第一信号线; 当所述第一比较器耦合到所述第一信号线时，使用所述第一比较器将所述第一电压电平与参考电压进行比较; 并且调整电压摆幅的量以达到校准的电压摆幅水平。 此外，该方法包括在退出校准模式时将第一比较器与第一信号线主动隔离。 存储器件在退出校准模式时可在正常读取操作中操作。 在正常读取操作期间，第一输出驱动器可操作以根据校准的电压摆幅电平将数据输出到第一信号线上。

    Method and apparatus for writing to memory components
    8.
    发明授权
    Method and apparatus for writing to memory components 失效
    用于写入存储器组件的方法和装置

    公开(公告)号：US5680361A

    公开(公告)日：1997-10-21

    申请号：US389561

    申请日：1995-02-14

    申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

    发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

    IPC分类号： G11C7/10 ,  G11C11/401

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

    摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

    摘要翻译： 提供附加模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

    Method and apparatus for writing to memory components
    9.
    发明授权
    Method and apparatus for writing to memory components 失效
    用于写入存储器组件的方法和装置

    公开(公告)号：US5940340A

    公开(公告)日：1999-08-17

    申请号：US858068

    申请日：1997-05-16

    申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

    发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

    IPC分类号： G11C7/10 ,  G11C11/401

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

    摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

    摘要翻译： 提供额外的操作模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。