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1.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 失效具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
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2.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 有权具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5909396A
公开(公告)日：1999-06-01
申请号：US127991
申请日：1998-08-03
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
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公开(公告)号：US08687403B1
公开(公告)日：2014-04-01
申请号：US13157713
申请日：2011-06-10
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C11/005 , G11C13/0007 , G11C13/0011 , G11C14/0045 , G11C14/009
摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
摘要翻译： 集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。 存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。 存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。
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4.发明授权Reconfigurable memory arrays having programmable impedance elements and corresponding methods 有权具有可编程阻抗元件和相应方法的可重构存储器阵列公开(公告)号：US08331128B1
公开(公告)日：2012-12-11
申请号：US12629531
申请日：2009-12-02
CPC分类号： G11C13/0069 , G11C7/00 , G11C8/16 , G11C11/005 , G11C11/404 , G11C11/56 , G11C11/5642 , G11C13/0004 , G11C13/0011 , G11C13/0035 , G11C13/004 , G11C13/0097 , G11C14/0045 , G11C29/816
摘要： A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.
摘要翻译： 存储器件可以包括多个存储器单元，每个存储单元具有至少一个固体离子导体的元件，所述固体离子导体可在至少两个不同的阻抗状态之间编程用于至少两个不同的数据保持时间，所述多个存储器单元可分为多个部分， 每个部分可以单独配置用于数据保留时间之一。
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公开(公告)号：US08294488B1
公开(公告)日：2012-10-23
申请号：US12767732
申请日：2010-04-26
IPC分类号： H03K19/173
CPC分类号： G11C13/0069 , H03K19/02 , H03K19/17736
摘要： An integrated circuit may include a plurality of sub bit line groups, each sub bit line group coupled to a different main bit line by a corresponding access device; and a plurality of programmable impedance elements arranged into element groups, each element group being coupled to a corresponding each sub bit line.
摘要翻译： 集成电路可以包括多个子位线组，每个子位线组由相应的访问设备耦合到不同的主位线; 以及布置成元件组的多个可编程阻抗元件，每个元件组耦合到对应的每个子位线。
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公开(公告)号：US06369433B1
公开(公告)日：2002-04-09
申请号：US09182525
申请日：1998-10-30
申请人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
发明人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang
IPC分类号： H01L2994
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823814 , H01L29/1041 , H01L29/66825
摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.
摘要翻译： 形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。
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公开(公告)号：US06177322B1
公开(公告)日：2001-01-23
申请号：US09177817
申请日：1998-10-23
申请人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1033 , H01L29/41775
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.
摘要翻译： 形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入 代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。
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8.发明授权High voltage transistor with high gated diode breakdown, low body effect and low leakage 有权具有高门极二极管击穿的高压晶体管，低体积效应和低漏电流
公开(公告)号：US6143612A
公开(公告)日：2000-11-07
申请号：US172090
申请日：1998-10-14
申请人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhacobian , Pau-ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L21/336 , H01L21/762 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/76216 , H01L29/0692 , H01L29/66659 , H01L29/78
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
摘要翻译： 强制显示高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。 在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。
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公开(公告)号：US06567303B1
公开(公告)日：2003-05-20
申请号：US10050483
申请日：2002-01-16
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445
摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。
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10.发明授权Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间公开(公告)号：US06549466B1
公开(公告)日：2003-04-15
申请号：US09657143
申请日：2000-09-07
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.
摘要翻译： 在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能 。 在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。 对于程序中的初始擦除周期，施加初始负栅极电压。 在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。 在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。 在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。
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