公开(公告)号：US06072725A

公开(公告)日：2000-06-06

申请号：US237257

申请日：1999-01-26

申请人： Binh Quang Le ,  Shane Charles Hollmer ,  Pau-ling Chen

发明人： Binh Quang Le ,  Shane Charles Hollmer ,  Pau-ling Chen

IPC分类号： G11C5/14 ,  G11C16/04

CPC分类号： G11C5/147

摘要： A method and an apparatus are provided for the production and supply of an erase voltage for the initial erasing operation of a floating gate transistor used as a capacitor in a voltage regulator, along with the proper electrical connection of the capacitor's control gate and commonly connected regions. In one embodiment, a capacitor erase control circuit controls a pass transistor for connecting the control gate of the floating gate capacitor to ground and another pass transistor for isolating the commonly connected source, drain and channel regions of the floating gate capacitor (the "well node") from ground. The erase control circuit simultaneously applies a capacitor erase input and a clock input to an erase voltage pass circuit to control a third pass transistor to apply an erase voltage to the well node, thereby erasing the floating gate capacitor. The erase control circuit and erase voltage pass circuit are formed on the same semiconductor substrate as the floating gate capacitor and the other components of the voltage regulator. The erasing methodology and apparatus enables economical implementation of an improved voltage regulator using a floating gate transistor.

摘要翻译： 提供了一种方法和装置，用于生产和提供用于在电压调节器中用作电容器的浮栅晶体管的初始擦除操作的擦除电压以及电容器的控制栅极和公共连接区域的适当电连接 。 在一个实施例中，电容器擦除控制电路控制用于将浮栅电容器的控制栅极连接到地的通过晶体管和用于隔离浮置栅极电容器（“阱节点”）的公共连接的源极，漏极和沟道区域的另一个通过晶体管 “）从地面。 擦除控制电路同时向擦除电压通过电路施加电容器擦除输入和时钟输入，以控制第三传输晶体管，以向阱节点施加擦除电压，从而擦除浮置栅极电容器。 擦除控制电路和擦除电压通过电路形成在与浮置栅极电容器和电压调节器的其它部件相同的半导体衬底上。 擦除方法和装置能够经济地实现使用浮栅晶体管的改进的稳压器。

公开(公告)号：US6005804A

公开(公告)日：1999-12-21

申请号：US993634

申请日：1997-12-18

申请人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

发明人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-ling Chen

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.

摘要翻译： EEPROM NAND阵列具有串联耦合的浮动栅极存储单元，每个浮动栅极存储单元在浮置栅极和体区之间具有控制栅极，浮动栅极，体区域和绝缘层。 负电荷泵耦合到身体区域。 在编程中，选择用于编程的存储单元的主体区域被负电荷泵偏置到负电压，而存储单元的控制栅极被偏置到预定的正电压以足以引导来自身体区域的Fowler-Nordheim隧穿 进入浮动门。 本发明允许NAND EEPROM存储单元的控制栅极上的编程电压要求显着降低，这允许NAND EEPROM阵列中的外围电压传送电路被设计为比传统的NAND EEPROM阵列更低的电压。

公开(公告)号：US06690602B1

公开(公告)日：2004-02-10

申请号：US10119391

申请日：2002-04-08

申请人： Binh Quang Le ,  Pau-ling Chen

发明人： Binh Quang Le ,  Pau-ling Chen

IPC分类号： G11C1134

CPC分类号： G11C16/107 ,  G11C16/0475 ,  G11C16/3409 ,  G11C2216/18

摘要： A method of cycling dual bit flash memory arrays having a plurality of dual bit flash memory cells arranged in a plurality of sectors with each sector having an associated reference array that have dual bit flash memory cells that are cycled with the plurality of dual bit flash memory cells in the sectors. The dual bit flash memory cells in the associated reference array are then programmed.

摘要翻译： 一种循环双位闪存阵列的方法，其具有布置在多个扇区中的多个双位闪存单元，每个扇区具有相关联的参考阵列，该参考阵列具有与多个双位闪存循环的双位闪存单元 细胞在行业。 然后对相关参考阵列中的双位闪存单元进行编程。

公开(公告)号：US5978266A

公开(公告)日：1999-11-02

申请号：US24880

申请日：1998-02-17

申请人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

发明人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.

摘要翻译： 提供了一种用于在编程期间偏置NAND阵列EEPROM以允许阵列在进入穿透之前被进一步缩小的方法。 NAND阵列的接地选择晶体管的源极被偏置为Vcc而不是接地，以减小接地选择晶体管的源极和漏极两端的电压降。 结果，在获得穿通之前，可以进一步缩短接地选择晶体管的沟道长度，从而产生更高密度的EEPROM。

公开(公告)号：US6143612A

公开(公告)日：2000-11-07

申请号：US172090

申请日：1998-10-14

申请人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/76216 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/78

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 强制显示高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。 在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US6081455A

公开(公告)日：2000-06-27

申请号：US232023

申请日：1999-01-14

申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12 ,  G11C16/00

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12

摘要： A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

摘要翻译： 块解码器包括p阱。 低电压源耦合到p阱，用于断定对p阱的体偏置电压。 n型字线传输晶体管位于p阱内并耦合到字线，用于将编程电压传递到字线。 耦合高电压源以通过配置成断定传输晶体管的栅极上的电压的电路。 低电压源被配置为在编程期间向p阱施加大约10伏特或更高的电压，从而降低位于p内的NMOS晶体管的源极和体区之间的电压（以及阈值电压） -好。 因此，需要施加到传输晶体管的电压量减小。 此外，通过电路可以用于较低的电源电压，因为电源电压受p阱内n型晶体管的阈值电压的限制。

公开(公告)号：US06369433B1

公开(公告)日：2002-04-09

申请号：US09182525

申请日：1998-10-30

申请人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang

发明人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang

IPC分类号： H01L2994

CPC分类号： H01L29/66575 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1041 ,  H01L29/66825

摘要： A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.

摘要翻译： 形成具有低泄漏和低体效应的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括在通道区域上提供场注入阻挡掩模，从而产生具有低体效应的晶体管，场注入阻挡掩模具有适当的开口，使得场注入发生在通道的边缘，从而减少泄漏。

公开(公告)号：US06188113B1

公开(公告)日：2001-02-13

申请号：US09502347

申请日：2000-02-10

申请人： Narbeh Derhocobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhocobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L31119

CPC分类号： H01L29/66575 ,  H01L21/76216 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/78

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。 在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US6009014A

公开(公告)日：1999-12-28

申请号：US90296

申请日：1998-06-03

申请人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

发明人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/344

摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

摘要翻译： 本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压 在擦除验证期间每个晶体管的控制栅极。 偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。 如果所有晶体管都不被擦除，则执行另一个擦除操作。 重复擦除直到擦除验证操作指示所有晶体管被正确擦除。 通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

公开(公告)号：US06137153A

公开(公告)日：2000-10-24

申请号：US23497

申请日：1998-02-13

申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

IPC分类号： H01L29/788 ,  H01L29/94 ,  H01L29/00

CPC分类号： H01L29/94 ,  H01L29/7881

摘要： A capacitor structure which exhibits a constant capacitance at non-negative voltages is provided by erasing a P-well floating gate NMOS transistor prior to its use as a capacitor. By erasing the transistor, a negative threshold voltage is obtained, thereby turning on the transistor and placing the transistor in an inversion state where the MOS capacitance is voltage-independent. Such transistors can be utilized as capacitors, whereby one plate of the capacitor corresponds to the control gate of the transistor and the other plate corresponds to the commonly connected source, drain, P-well, and deep N-well regions of the transistor, in voltage regulator circuits or other circuits in which node stabilization is desired. As a result, the capacitance is constant even at initialization when zero volts is applied.

摘要翻译： 在非负电压下呈现恒定电容的电容器结构通过在用作电容器之前擦除P阱浮置NMOS NMOS晶体管来提供。 通过擦除晶体管，获得负阈值电压，从而导通晶体管并将晶体管置于MOS电容与电压无关的反转状态。 这种晶体管可以用作电容器，由此电容器的一个板对应于晶体管的控制栅极，另一个板对应于晶体管的公共连接的源极，漏极，P阱和深N阱区域，其中 电压调节器电路或其中需要节点稳定的其他电路。 结果，即使在施加零伏特的初始化时，电容也是恒定的。