公开(公告)号：US09652259B2

公开(公告)日：2017-05-16

申请号：US14008196

申请日：2011-10-01

申请人： Blaise Fanning ,  Anil K. Sabbavarapu

发明人： Blaise Fanning ,  Anil K. Sabbavarapu

IPC分类号： G06F9/445 ,  G06F11/14

CPC分类号： G06F9/44505 ,  G06F11/1441 ,  Y02D10/43

摘要： The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.

公开(公告)号：US20090172429A1

公开(公告)日：2009-07-02

申请号：US11967920

申请日：2007-12-31

申请人： Ramana Rachakonda ,  Blaise Fanning ,  Anil K. Sabbavarapu ,  Belliappa M. Kuttanna ,  Rajesh Patel ,  Kenneth D. Shoemaker ,  Lance E. Hacking ,  Bruce L. Fleming ,  Ashish V. Choubal

发明人： Ramana Rachakonda ,  Blaise Fanning ,  Anil K. Sabbavarapu ,  Belliappa M. Kuttanna ,  Rajesh Patel ,  Kenneth D. Shoemaker ,  Lance E. Hacking ,  Bruce L. Fleming ,  Ashish V. Choubal

IPC分类号： G06F1/26

CPC分类号： G06F1/3203

摘要： In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

摘要翻译： 在一些实施例中，提供上电（或功率模式）接口，由此芯片的上电信号被编码为多个状态以提供比用于定义状态的信号的数量更多的功能。

公开(公告)号：US07437634B2

公开(公告)日：2008-10-14

申请号：US10436775

申请日：2003-05-13

申请人： Talal K. Jaber ,  Anil K. Sabbavarapu

发明人： Talal K. Jaber ,  Anil K. Sabbavarapu

IPC分类号： G01R31/28 ,  H03K3/289

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.

摘要翻译： 顺序扫描单元包括用于功能数据的输入端口和用于扫描测试数据的输入端。 用于扫描测试数据的输入是耦合到定义扫描测试电路的从扫描触发器的主扫描触发器的输入。 这种扫描测试电路耦合到顺序扫描单元的功能电路，使得功能信号的路径不通过扫描测试电路，对功能信号不施加任何性能损失。 扫描测试数据通过两个非重叠的扫描时钟扫描顺序单元格，并且仅在系统功能时钟处于关闭状态时处于活动状态。

公开(公告)号：US07216274B2

公开(公告)日：2007-05-08

申请号：US10609254

申请日：2003-06-26

申请人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

发明人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

IPC分类号： G01R31/28

CPC分类号： G01R31/318552 ,  G01R31/318594 ,  G06F11/2236

摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

摘要翻译： 用于测试复杂集成电路的测试架构，其中每个功能单元可以独立于其他功能单元进行测试。 本发明的实施例允许功能单元的测试以比处理器的其它部分更慢或更快的时钟速度发生，而不会引起延迟或其他不利的定时效应。

公开(公告)号：US06815977B2

公开(公告)日：2004-11-09

申请号：US10328203

申请日：2002-12-23

申请人： Anil K. Sabbavarapu ,  Talal K. Jaber ,  Grant W. McFarland ,  Paven R. Sunkerneni ,  David M. Wu

发明人： Anil K. Sabbavarapu ,  Talal K. Jaber ,  Grant W. McFarland ,  Paven R. Sunkerneni ,  David M. Wu

IPC分类号： H03K1900

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.

摘要翻译： 根据一些实施例，电路包括Domino状态元件，主锁存器，用于接收第一时钟信号并且响应于第一时钟信号在Domino状态元件中存储值;以及从锁存器，用于接收第二时钟信号 并且响应于第二时钟信号而输出该值。 一些实施例提供耦合到第一节点的第一状态单元，耦合到第一状态单元的主锁存器，主锁存器以接收第一存储信号，第一负载信号，第一时钟信号和第一扫描值信号， 耦合到第二节点的第二状态元件，连接到第一节点的第二节点和耦合到第二状态元件的从锁存器，从锁存器接收第二存储信号，第二负载信号，第二时钟信号和 第二扫描值信号。