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    Method, system and apparatus for low-power storage of processor context information
    3.
    发明授权
    Method, system and apparatus for low-power storage of processor context information 有权
    用于处理器上下文信息的低功率存储的方法，系统和装置

    公开(公告)号：US08352770B2

    公开(公告)日：2013-01-08

    申请号：US12567707

    申请日：2009-09-25

    申请人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    发明人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3287 ,  G06F1/3203

    摘要： A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

    摘要翻译： 一种用于保存和/或检索用于电力状态转换的处理器核心的上下文信息的方法和系统。 处理器核心驻留在多个功率状态之间不同地转换的复杂功率域。 处理器核心包括用于存储和检索处理器核心上下文信息的本地上下文存储区域。 低功耗上下文存储位于复合功率域外的标称功率域。 基于复电力域的功率状态转换是否包括向处理器核心断电的过渡，将处理器核心的上下文信息存储到低功率上下文存储器。

    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION
    4.
    发明申请
    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION 有权
    用于处理器上下文信息的低功率存储的方法，系统和装置

    公开(公告)号：US20110078463A1

    公开(公告)日：2011-03-31

    申请号：US12567707

    申请日：2009-09-25

    申请人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    发明人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1/00 ,  G06F12/16

    CPC分类号： G06F1/3287 ,  G06F1/3203

    摘要： A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

    摘要翻译： 一种用于保存和/或检索用于电力状态转换的处理器核心的上下文信息的方法和系统。 处理器核心驻留在多个功率状态之间不同地转换的复杂功率域。 处理器核心包括用于存储和检索处理器核心上下文信息的本地上下文存储区域。 低功耗上下文存储位于复合功率域外的标称功率域。 基于复电力域的功率状态转换是否包括向处理器核心断电的过渡，将处理器核心的上下文信息存储到低功率上下文存储器。

    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION
    5.
    发明申请
    METHOD, SYSTEM AND APPARATUS FOR LOW-POWER STORAGE OF PROCESSOR CONTEXT INFORMATION 有权
    用于处理器上下文信息的低功率存储的方法，系统和装置

    公开(公告)号：US20130124898A1

    公开(公告)日：2013-05-16

    申请号：US13736829

    申请日：2013-01-08

    申请人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    发明人： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3203

    摘要： A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

    摘要翻译： 一种用于保存和/或检索用于电力状态转换的处理器核心的上下文信息的方法和系统。 处理器核心驻留在多个功率状态之间不同地转换的复杂功率域。 处理器核心包括用于存储和检索处理器核心上下文信息的本地上下文存储区域。 低功耗上下文存储位于复合功率域外的标称功率域。 基于复电力域的功率状态转换是否包括向处理器核心断电的过渡，将处理器核心的上下文信息存储到低功率上下文存储器。

    Method and system for efficiently fetching from cache during a cache fill operation
    6.
    发明授权
    Method and system for efficiently fetching from cache during a cache fill operation 失效
    高速缓存填充操作期间从高速缓存中有效提取的方法和系统

    公开(公告)号：US5897654A

    公开(公告)日：1999-04-27

    申请号：US881223

    申请日：1997-06-24

    申请人： Lee E. Eisen ,  Belliappa M. Kuttanna ,  Soummya Mallick ,  Rajesh B. Patel

    发明人： Lee E. Eisen ,  Belliappa M. Kuttanna ,  Soummya Mallick ,  Rajesh B. Patel

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0859 ,  G06F12/0862

    摘要： A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

    摘要翻译： 数据处理系统中的一种方法和系统，用于通过在多个数据字或指令被加载到高速缓存中允许读取器从高速缓冲存储器中读取来高效地与高速缓存存储器连接。 总线接口单元请求将多个指令或数据字加载到高速缓存中。 响应于由总线接口单元加载到高速缓存中的每个单独指令或数据字，存在所述多个指令或数据字中的单个指令或数据字有效的指示。 一旦所需的指令或数据字具有有效的指示，则在所有指令或数据字被加载到高速缓存之前，允许提取器完成取指操作。 在一个实施例中，一组无效标签位可以被用于在由总线接口单元写入高速缓存之后向读取器指示一组指令或数据字中的各个有效。

    Apparatus and method for bad address handling
    8.
    发明授权
    Apparatus and method for bad address handling 有权
    不良地址处理的装置和方法

    公开(公告)号：US06526485B1

    公开(公告)日：2003-02-25

    申请号：US09368008

    申请日：1999-08-03

    申请人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna

    发明人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1200

    CPC分类号： G06F9/3842 ,  G06F9/383 ,  G06F9/3861

    摘要： Circuitry including a request queue and a bad address handling circuit. The request queue includes an entry for each outstanding load requesting access to a cache. Each request queue entry includes a valid bit, an issue bit and a flush bit. The state of the valid bit indicates whether or not the associated access request should be issued to the cache. The issue bit indicates whether the load access request has been issued to the cache and the flush bit indicates whether the data retrieved from the cache in response to the request should be loaded into a specified register. The bad address handling circuit responds to a replay load request by manipulating the states of the valid or flush bit of the relevant request queue entry to prevent completion of bad consumer load requests. The bad address handling circuit includes a validation circuit and a flush circuit. The validation circuit alters the state of the valid bit of the relevant request queue entry in response to the replay load request based upon the state of issue bit for that request queue entry. If the issue bit indicates that the load access request has not yet been issued to the cache, then the validation circuit alters the state of the associated valid bit to prevent the issuance of that load access request to the cache. On the other hand, if the bad consumer has already been issued to the cache, then the flush circuit responds by altering the state of the flush bit to prevent the data retrieved from the cache in response to the bad consumer from being loaded into the register file.

    摘要翻译： 电路包括请求队列和不良地址处理电路。 请求队列包括每个未完成的负载请求访问高速缓存的条目。 每个请求队列条目包括有效位，发布位和刷新位。 有效位的状态指示是否应该向缓存发出关联的访问请求。 问题位指示加载访问请求是否已经发送到高速缓存，并且刷新位指示是否将响应于该请求从高速缓存检索的数据加载到指定的寄存器中。 坏地址处理电路通过操纵相关请求队列条目的有效或刷新位的状态来响应重放加载请求，以防止完成不良的消费者负载请求。 坏地址处理电路包括一个验证电路和一个冲洗电路。 响应于基于该请求队列条目的发布状态位的重放加载请求，验证电路改变相关请求队列条目的有效位的状态。 如果问题位指示加载访问请求尚未被发送到缓存，则验证电路改变相关联的有效位的状态，以防止向缓存发出该加载访问请求。 另一方面，如果坏消费者已经被发送到高速缓存，则刷新电路通过改变刷新位的状态来响应，以防止响应于坏消费者从缓存中检索的数据被加载到寄存器中 文件。

    Apparatus and method for preventing cache data eviction during an atomic operation
    9.
    发明授权
    Apparatus and method for preventing cache data eviction during an atomic operation 有权
    用于在原子操作期间防止高速缓存数据驱逐的装置和方法

    公开(公告)号：US06347360B1

    公开(公告)日：2002-02-12

    申请号：US09513033

    申请日：2000-02-25

    申请人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna ,  Allan Tzeng

    发明人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna ,  Allan Tzeng

    IPC分类号： G06F1200

    CPC分类号： G06F12/126 ,  G06F12/0831

    摘要： Apparatus and method for protecting cache data from eviction during an atomic operation. The apparatus includes a first request queue, a second request queue, and an atomic address block. The first request queue stores an entry for each cache access request. Each entry includes a first set of address bits and an atomic bit. The first set of address bits represents a first cache address associated with the cache access request and the atomic bit indicates whether the cache access request is associated with the atomic operation. The second request queue stores an entry for each cache eviction request. Each entry of the second request queue includes a second set of address bits indicating a second cache address associated with the cache eviction request. The atomic address block prevents eviction of a third cache address during the atomic operation on the third cache address. During a first clock cycle the atomic address block receives and analyzes a first set of signals representing a first entry of the first request queue to determine whether they represent the atomic operation. If so, the atomic address block sets a third set of address bits to a value representative of the first cache address. During a second clock cycle during which the atomic operation is being executed the atomic address block receives and analyzes a second set of signals representing the second set of address bits to determine whether the second set of address bits represent a same cache address as the third set of address bits. If so, the atomic address block stalls servicing of the second request queue, thus preventing eviction of data from the cache upon which an atomic operation is being performed.

    摘要翻译： 用于在原子操作期间保护缓存数据免于驱逐的装置和方法。 该装置包括第一请求队列，第二请求队列和原子地址块。 第一个请求队列存储每个缓存访问请求的条目。 每个条目包括第一组地址位和原子位。 第一组地址位表示与高速缓存访​​问请求相关联的第一高速缓存地址，并且原子位指示高速缓存访​​问请求是否与原子操作相关联。 第二个请求队列存储每个缓存逐出请求的条目。 第二请求队列的每个条目包括指示与缓存驱逐请求相关联的第二高速缓存地址的第二组地址位。 原子地址块防止在第三高速缓存地址的原子操作期间驱逐第三高速缓存地址。 在第一时钟周期期间，原子地址块接收并分析表示第一请求队列的第一条目的第一组信号，以确定它们是否表示原子操作。 如果是，则原子地址块将第三组地址位设置为表示第一高速缓存地址的值。 在原子操作正在执行的第二时钟周期期间，原子地址块接收并分析表示第二组地址位的第二组信号，以确定第二组地址位是否表示与第三组相同的高速缓存地址 的地址位。 如果是，则原子地址块停止对第二请求队列的服务，从而防止从正在执行原子操作的高速缓存的数据的驱逐。

    Apparatus and method to prevent overwriting of modified cache entries prior to write back
    10.
    发明授权
    Apparatus and method to prevent overwriting of modified cache entries prior to write back 有权
    在回写前防止修改缓存条目覆盖的装置和方法

    公开(公告)号：US06286082B1

    公开(公告)日：2001-09-04

    申请号：US09294939

    申请日：1999-04-19

    申请人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna

    发明人： Anuradha N. Moudgal ,  Belliappa M. Kuttanna

    IPC分类号： G06F1316

    CPC分类号： G06F12/0804

    摘要： A hazard control circuit for a cache controller that prevents overwriting of modified cache data without write back. The cache controller controls a non-blocking, N-way set associative cache that uses a write-back cache-coherency protocol. The hazard control circuit prevents data loss by deferring assignment until after completion of a pending fill for that way. The hazard control circuit of the present invention includes a transit hazard buffer, a stall assertion circuit and a way assignment circuit.

    摘要翻译： 用于缓存控制器的危险控制电路，防止在不回写的情况下重写修改的高速缓存数据。 高速缓存控制器控制使用回写高速缓存一致性协议的非阻塞N路组关联高速缓存。 危险控制电路通过延迟分配来防止数据丢失，直到完成等待填充为止。 本发明的危害控制电路包括转接危险缓冲器，失速断言电路和方式分配电路。