公开(公告)号：US20220302362A1

公开(公告)日：2022-09-22

申请号：US17556224

申请日：2021-12-20

Applicant: BOE MLED Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Linhui GONG ,  Liang SUN ,  Chao LIU ,  Sha FENG

IPC: H01L33/62 ,  H01L27/15

Abstract: The present disclosure provides a display panel and a manufacturing method thereof, a display apparatus and a splicing display apparatus. The display panel includes: a back plate, at least one connection lead and a first protection layer. Each of the at least one connection lead includes a main conductive layer. The first protection layer includes a first portion on two sides of the main conductive layer of the connection lead in a width direction thereof.

公开(公告)号：US20170168330A1

公开(公告)日：2017-06-15

申请号：US15322549

申请日：2016-04-15

Applicant: Boe Technology Group Co., Ltd.

Inventor： Zuqiang WANG ,  Guang LI ,  Liang SUN ,  Xiaoyong LU

IPC: G02F1/13 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/32 ,  G01R31/28

CPC classification number: G02F1/1309 ,  G01R31/2825 ,  G02F1/133345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136254 ,  G02F2001/136295 ,  G09G3/006 ,  G09G3/3208 ,  G09G2300/0417 ,  H01L21/77 ,  H01L22/34 ,  H01L27/3262 ,  H01L2227/323

Abstract: A display panel comprises a display area and a peripheral area around the display area. The peripheral area comprises: an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region comprises a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region comprises a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

公开(公告)号：US20160300957A1

公开(公告)日：2016-10-13

申请号：US15084802

申请日：2016-03-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong LU ,  Zheng LIU ,  Xiaolong LI ,  Dong LI ,  Huijuan ZHANG ,  Liang SUN

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L29/78675 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: The embodiments of the present invention disclose a low temperature (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; agate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.

Abstract translation: 本发明的实施例公开了低温（LTPS）晶体管阵列基板及其制造方法以及显示装置。 LTPS晶体管阵列基板包括基板; 设置在所述基板上的多晶硅半导体有源区; 与多晶硅半导体有源区绝缘的玛瑙; 以及设置在所述栅极的侧壁上的电介质间隔区，其中与所述电介质间隔区相对应的所述多晶硅半导体有源区的一部分包括缓冲区，并且所述电介质间隔区围绕所述栅极的侧壁 缓冲区。

公开(公告)号：US20140168559A1

公开(公告)日：2014-06-19

申请号：US14108856

申请日：2013-12-17

Applicant: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaming ZHU ,  Liang SUN ,  Jianfeng YUAN ,  Seung Moo RIM ,  Xibin SHAO

IPC: G02F1/1333 ,  H01L27/12

CPC classification number: G02F1/136204 ,  H01L27/124

Abstract: According to one aspect of the present invention, the provided is an array substrate. Specifically, the first conductive strip that is coupled to the first data shorting bar and the second conductive strip that is coupled to the second data shorting bar are formed on the array substrate. The width of the first conductive strip is greater than the width of the first data shorting bar. The width of the second conductive strip is greater than the width of the second data shorting bar. The first conductive strip is overlapped with the second conductive strip. Such a structure of the array substrate effectively increases the overlapped capacitance between the data metal layer and the gate metal layer.

Abstract translation: 根据本发明的一个方面，提供了一种阵列基板。 具体地，耦合到第一数据短路棒的第一导电条和耦合到第二数据短路棒的第二导电条形成在阵列基板上。 第一导电条的宽度大于第一数据短路条的宽度。 第二导电条的宽度大于第二数据短路条的宽度。 第一导电带与第二导电带重叠。 阵列基板的这种结构有效地增加了数据金属层与栅极金属层之间的重叠电容。

公开(公告)号：US20240274763A1

公开(公告)日：2024-08-15

申请号：US18561741

申请日：2021-05-27

Applicant: BOE MLED Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Enkai DONG ,  Liang SUN ,  Jiacheng QI

IPC: H01L33/54 ,  G02F1/1335 ,  G02F1/13357

CPC classification number: H01L33/54 ,  G02F1/133603 ,  G02F1/133612

Abstract: A backlight module comprises a driving backplate, which comprises a multiple pads; multiple light-emitting diodes, which are electrically connected to the pads; and multiple transparent protection structures, which are located on the sides of the multiple light-emitting diodes that are away from the driving backplate, wherein the transparent protection structures cover the light-emitting diodes, there is a first distance between the center of the orthographic projection of each transparent protection structure on the driving backplate and the center of the orthographic projection of each light-emitting diode on the driving backplate; and the length of the orthographic projection of each light-emitting diode on the driving backplate is a second distance, the width of the orthographic projection of each light-emitting diode on the driving backplate is a third distance, the ratio of the first distance to the second distance is less than or equal to 1:2-1:10.

公开(公告)号：US20190237518A1

公开(公告)日：2019-08-01

申请号：US16358819

申请日：2019-03-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liang SUN ,  Tuo SUN ,  Xiaodan JIN ,  Lintao ZHANG

IPC: H01L27/32 ,  H01L51/50

CPC classification number: H01L27/3211 ,  H01L27/3246 ,  H01L51/5012

Abstract: A display panel includes pixels arranged in an array in a first direction and a second direction. Each pixel includes a first sub-pixel having a first light-emitting zone to emit light of a first color, a second sub-pixel having a second light-emitting zone to emit light of a second color, and a third sub-pixel having a third light-emitting zone to emit light of a third color. The first, second, and third light-emitting zones are arranged in a triangle such that the first, second, and third light-emitting zones cover respective vertices of the triangle, with one side of the triangle being substantially parallel to the first direction. Any two pixels directly adjacent in the first direction have respective patterns of first, second, and third light-emitting zones, which are substantially mirror-symmetrical to each other. Any two diagonally adjacent pixels have a substantially repeating pattern of first, second and third light-emitting zones.

公开(公告)号：US20180175121A1

公开(公告)日：2018-06-21

申请号：US15127215

申请日：2015-10-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Fengli JI ,  Yinan LIANG ,  Shanshan BAI ,  Minghua XUAN ,  Liang SUN

IPC: H01L27/32 ,  H01L51/52

CPC classification number: H01L27/3218 ,  H01L27/3246 ,  H01L51/52

Abstract: A pixel arrangement structure, an organic electroluminescent device (i.e., organic light-emitting diode device), a display device and a mask are provided, which can increase opening areas of a metal mask for forming the pixel arrangement structure, and improve the aperture ratio, the brightness, the service life and the image resolution of active matrix organic light-emitting diode (AMOLED) products. The pixel arrangement structure includes a plurality of pixels. Each pixel includes three sub-pixels of different colors; connecting lines of center points of the sub-pixels form equilateral triangles; and each sub-pixel has a shape of polygon with more than four sides.

公开(公告)号：US20170116917A1

公开(公告)日：2017-04-27

申请号：US15032277

申请日：2015-07-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liang SUN

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/045

Abstract: The present disclosure discloses an OLED pixel circuit, a display apparatus, and a control method. The OLED pixel circuit includes an OLED; a driving transistor a drain electrode of which is connected with the OLED; a first switching unit configured to output, during a light-emitting stage, a power source signal to a source electrode of the driving transistor; a second switching unit configured to output, during a present scanning stage, a data signal to a gate electrode of the driving transistor; a compensation unit having a capacitor, and a charging control unit configured to output, during a charging stage, a charging signal to the capacitor for charging the capacitor so that the capacitor can maintain, during the light-emitting stage, a voltage of the gate electrode of the driving transistor. The charging signal has a voltage value greater than an actual voltage value of the data signal.

公开(公告)号：US20160267843A1

公开(公告)日：2016-09-15

申请号：US14650687

申请日：2014-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ying WANG ,  Xinshe YIN ,  Guang LI ,  Liang SUN

IPC: G09G3/3258 ,  G09G3/3291 ,  G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0278 ,  G09G2320/045 ,  G09G2330/028

Abstract: A pixel driving circuit and a driving method thereof, and an array substrate are provided. The pixel driving circuit includes a data line (Data), a gate line (Gate), a first power supply line (ELVDD), a second power supply line (ELVSS), a reference signal line (ref), a light emitting device (D), a driving transistor (T7), a storage capacitor (C1), a reset unit, a data writing unit, a compensating unit and a light emitting control unit. The pixel driving circuit can compensate and remove non-uniformity in displaying caused by variances in threshold voltage among driving transistors.

Abstract translation: 提供像素驱动电路及其驱动方法以及阵列基板。 像素驱动电路包括数据线（Data），栅极线（Gate），第一电源线（ELVDD），第二电源线（ELVSS），参考信号线（ref），发光器件 D），驱动晶体管（T7），存储电容器（C1），复位单元，数据写入单元，补偿单元和发光控制单元。 像素驱动电路可以补偿和消除由驱动晶体管之间的阈值电压的方差引起的显示不均匀性。

公开(公告)号：US20160254389A1

公开(公告)日：2016-09-01

申请号：US14768349

申请日：2015-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong LU ,  Zheng LIU ,  Liang SUN ,  Xiaolong LI ,  Chunping LONG

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L27/12

CPC classification number: H01L29/78618 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

Abstract: A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.

Abstract translation: 提供一种低温多晶硅薄膜晶体管及其制造方法，阵列基板和显示装置。 该方法包括：S1：在基底（1）上依次形成有源层（3），栅极绝缘层（4），栅电极（5）和层间绝缘层（6）; S2：形成第一金属薄膜层（8）; S3：在有源层（3）和栅极绝缘层（6）上进行氢化处理; S4：形成第二金属薄膜层（7），第二金属薄膜层（7）用于形成源电极和漏电极。