摘要:
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.
摘要:
A technique to filter bogus instructions from a processor pipeline. At least one embodiment of the invention detects a bogus event, removes only instructions from the processor corresponding to the bogus event without affecting instructions not corresponding to the bogus event.
摘要:
A device, system, and method are disclosed. In one embodiment device includes routing logic that is capable of receiving an I/O storage request from an operating system. The I/O storage request includes an input/output (I/O) data type tag that specifies a type of I/O data to be stored with the I/O storage request. The routing logic is also capable of determining, based on the I/O data type tag, which of a number of storage pools to send the I/O storage request. Each storage pool has a certain level of associated service.
摘要:
A method according to one embodiment may include partitioning a multi-core processor into a first partition and a second partition, the first partition including a first processor core and a first interrupt controller configured to store a first partition identifier, the second partition including a second processor core and a second interrupt controller configured to store a second partition identifier. The method may also include receiving, by the first interrupt controller and the second interrupt controller, at least one interrupt that includes a partition identifier. The method may also include comparing, by the first interrupt controller, the partition identifier included with the interrupt to the first partition identifier stored in the first interrupt controller.
摘要:
A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.
摘要:
A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.
摘要:
Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.
摘要:
A memory region access management technique. More particularly, at least one embodiment of the invention relates to a technique to partition memory between two or more operating systems or other software running on one or more processors.
摘要:
Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.