公开(公告)号：US20080034190A1

公开(公告)日：2008-02-07

申请号：US11891076

申请日：2007-08-08

申请人： Dion Rodgers ,  Deborah Marr ,  David Hill ,  Shiv Kaushik ,  James Crossland ,  David Koufaty

发明人： Dion Rodgers ,  Deborah Marr ,  David Hill ,  Shiv Kaushik ,  James Crossland ,  David Koufaty

IPC分类号： G06F9/30

CPC分类号： G06F9/3009 ,  G06F9/30079 ,  G06F9/3851 ,  G06F9/4812 ,  G06F9/4843

摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

公开(公告)号：US20070162774A1

公开(公告)日：2007-07-12

申请号：US11716377

申请日：2007-03-09

申请人： Per Hammarlund ,  James Crossland ,  Anil Aggarwal ,  Shivnandan Kaushik

发明人： Per Hammarlund ,  James Crossland ,  Anil Aggarwal ,  Shivnandan Kaushik

IPC分类号： G06F1/00

CPC分类号： G06F9/526 ,  G06F1/3203 ,  G06F9/3004 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3851

摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 根据一个实施例，监视与竞争锁相关联的节点; 并且寻求有争议的锁的处理器进入休眠状态直到发生监视事件。

公开(公告)号：US20070061634A1

公开(公告)日：2007-03-15

申请号：US11227831

申请日：2005-09-15

申请人： Suresh Marisetty ,  Andrew Fish ,  Koichi Yamada ,  Scott Brenden ,  James Crossland ,  Shivnandan Kaushik ,  Mohan Kumar ,  Jose Vargas

发明人： Suresh Marisetty ,  Andrew Fish ,  Koichi Yamada ,  Scott Brenden ,  James Crossland ,  Shivnandan Kaushik ,  Mohan Kumar ,  Jose Vargas

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0706

摘要： Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

摘要翻译： 使用协调操作系统（OS）和固件服务执行硬件错误处理的方法和架构。 在一个方面，提供固件接口以使OS能够访问固件错误处理服务。 这样的服务使得OS能够访问有关平台硬件错误的错误数据，这些错误数据可能不会通过平台处理器或其他常规方法被定向访问。 还公开了用于在使用基于OS的服务尝试服务错误之前拦截硬件错误事件的处理以及将控制引导到固件错误处理服务的技术。 固件服务可以纠正OS稍后访问或使用带外通信信道提供给远程管理服务器的硬件错误和/或日志错误数据。 根据另一方面，固件拦截和服务可以以对OS是透明的方式来执行。

公开(公告)号：US20070143514A1

公开(公告)日：2007-06-21

申请号：US11704760

申请日：2007-02-09

申请人： Shivnandan Kaushik ,  John Horigan ,  Alon Naveh ,  James Crossland

发明人： Shivnandan Kaushik ,  John Horigan ,  Alon Naveh ,  James Crossland

IPC分类号： G06F13/24 ,  G06F1/00

CPC分类号： G06F9/3851 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/4812 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D10/24

摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。

公开(公告)号：US20050149314A1

公开(公告)日：2005-07-07

申请号：US10749929

申请日：2003-12-29

申请人： Lily Looi ,  Stanley Kulick ,  Dean Mulla ,  Ashish Gupta ,  Keith Pflederer ,  Shivnandan Kaushik ,  Mohan Kumar ,  James Crossland

发明人： Lily Looi ,  Stanley Kulick ,  Dean Mulla ,  Ashish Gupta ,  Keith Pflederer ,  Shivnandan Kaushik ,  Mohan Kumar ,  James Crossland

IPC分类号： G06F9/455 ,  G06F11/20 ,  G06F13/16

CPC分类号： G06F11/1666 ,  G06F13/16

摘要： In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

摘要翻译： 在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟 一个扩展记忆桥。 在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。

公开(公告)号：US20050027914A1

公开(公告)日：2005-02-03

申请号：US10631522

申请日：2003-07-31

申请人： Per Hammalund ,  James Crossland ,  Shivnandan Kaushik ,  Anil Aggarwal

发明人： Per Hammalund ,  James Crossland ,  Shivnandan Kaushik ,  Anil Aggarwal

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F15/167 ,  G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/544

摘要： According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

摘要翻译： 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。

公开(公告)号：US20080022141A1

公开(公告)日：2008-01-24

申请号：US11903249

申请日：2007-09-20

申请人： Per Hammarlund ,  James Crossland ,  Anil Aggarwal ,  Shivnandan Kaushik

发明人： Per Hammarlund ,  James Crossland ,  Anil Aggarwal ,  Shivnandan Kaushik

IPC分类号： G06F1/32

CPC分类号： G06F9/526 ,  G06F1/3203 ,  G06F9/3004 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3851

摘要： A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.

摘要翻译： 提供了一种使用监视器 - 内存等待监视锁定的方法，装置和系统。 在一个实施例中，提供了存储用于执行监视机制的功能的指令的存储器。 监视机制具有使处理器响应于事件退出休眠状态的第一逻辑，其中退出休眠状态包括恢复处理在休眠状态期间被处理器放弃的处理资源的控制。 所述监视机制具有第二逻辑，以在所述处理器退出所述睡眠状态之后禁用与竞争锁相关联的节点的监视。

公开(公告)号：US20060294347A1

公开(公告)日：2006-12-28

申请号：US11134687

申请日：2005-05-19

申请人： Xiang Zou ,  Hong Wang ,  Scott Rodgers ,  Darrell Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry Smith ,  James Crossland ,  Chris Newburn

发明人： Xiang Zou ,  Hong Wang ,  Scott Rodgers ,  Darrell Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry Smith ,  James Crossland ,  Chris Newburn

IPC分类号： G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US20060143333A1

公开(公告)日：2006-06-29

申请号：US11026928

申请日：2004-12-29

申请人： Dave Minturn ,  James Crossland ,  Sujoy Sen ,  Greg Cummings

发明人： Dave Minturn ,  James Crossland ,  Sujoy Sen ,  Greg Cummings

IPC分类号： G06F5/00 ,  G06F12/00

CPC分类号： G06F12/0875 ,  G06F12/0862

摘要： The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.