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1.发明申请公开(公告)号：US20080272457A1
公开(公告)日：2008-11-06
申请号：US11744248
申请日：2007-05-04
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/823481 , H01L27/0207 , H01L27/0617 , H01L27/08 , H01L27/1203
摘要： A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面的衬底，（b）衬底上的N个半导体区域，以及（c）衬底上的P个半导体区域，N和P 正整数。 N个半导体区域包括掺杂剂。 P半导体区域不包含掺杂剂。 该结构还包括在衬底的顶部上的M个互连层，N个半导体区域和P个半导体区域，M是正整数。 M互连层包括电感器。 （i）N个半导体区域不重叠，（ii）P个半导体区域在参考方向上与电感器重叠。 垂直于基准方向并且与N个半导体区域的半导体区域交叉的平面与P半导体区域的半导体区域相交。
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公开(公告)号：US07791166B2
公开(公告)日：2010-09-07
申请号：US11744248
申请日：2007-05-04
IPC分类号： H01L29/00
CPC分类号： H01L21/84 , H01L21/823481 , H01L27/0207 , H01L27/0617 , H01L27/08 , H01L27/1203
摘要： A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面的衬底，（b）衬底上的N个半导体区域，以及（c）衬底上的P个半导体区域，N和P 正整数。 N个半导体区域包括掺杂剂。 P半导体区域不包含掺杂剂。 该结构还包括在衬底的顶部上的M个互连层，N个半导体区域和P个半导体区域，M是正整数。 M互连层包括电感器。 （i）N个半导体区域不重叠，（ii）P个半导体区域在参考方向上与电感器重叠。 垂直于基准方向并且与N个半导体区域的半导体区域交叉的平面与P半导体区域的半导体区域相交。
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公开(公告)号：US08586488B2
公开(公告)日：2013-11-19
申请号：US12860990
申请日：2010-08-23
IPC分类号： H01L21/00
CPC分类号： H01L21/268
摘要： A computer program product and system for configuring J electromagnetic radiation sources (J≧2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1−S1|, |W2−S2|, |WI−SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
摘要翻译： 一种用于配置J电磁辐射源（J> = 2）以同时照射衬底的计算机程序产品和系统。 每个源具有不同的发射辐射的波长和角分布的功能。 衬底包括基层，I堆叠（I> = 2）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 为了将I堆叠同时暴露于来自J源的辐射，计算Pj，使得误差E是| W1-S1 |，| W2-S2 |，| WI-SI |的函数; 相对于Pj（j = 1，...，J）被最小化。 Wi和Si分别表示通过堆叠i（i = 1，...，I）传输到衬底中的实际和目标能量通量。 这些堆叠暴露于由所计算的Pj（j = 1，...，J）表征的源的辐射。
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公开(公告)号：US07399664B1
公开(公告)日：2008-07-15
申请号：US11679862
申请日：2007-02-28
IPC分类号： H01L21/84 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/4763 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66795
摘要： A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.
摘要翻译： 一种结构及其形成方法。 该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域 半导体鳍片区域的侧壁。 栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。 该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。 半导体鳍片区域的第一侧壁暴露于周围环境。 第一间隔区域的顶表面与栅电极区域的顶表面共面。
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5.发明申请FIELD EFFECT TRANSISTOR WITH THIN GATE ELECTRODE AND METHOD OF FABRICATING SAME 有权具有薄门电极的场效应晶体管及其制造方法公开(公告)号：US20080157188A1
公开(公告)日：2008-07-03
申请号：US12037121
申请日：2008-02-26
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与 所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度 厚度。
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6.发明授权Field effect transistor with thin gate electrode and method of fabricating same 有权具有薄栅电极的场效应晶体管及其制造方法公开(公告)号：US07374980B2
公开(公告)日：2008-05-20
申请号：US11549311
申请日：2006-10-13
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与 所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度 厚度。
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公开(公告)号：US20100318210A1
公开(公告)日：2010-12-16
申请号：US12860990
申请日：2010-08-23
IPC分类号： G06F17/00
CPC分类号： H01L21/268
摘要： A computer program product and system for configuring J electromagnetic radiation sources (J≧2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1−S1|, |W2−S2|, |WI−SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
摘要翻译： 一种用于配置J电磁辐射源（J≥2）以同时照射衬底的计算机程序产品和系统。 每个源具有不同的发射辐射的波长和角分布的功能。 基板包括基层和I堆叠（I≥2）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 为了将I堆叠同时暴露于来自J源的辐射，计算Pj，使得误差E是| W1-S1 |，| W2-S2 |，| WI-SI |的函数; 相对于Pj（j = 1，...，J）被最小化。 Wi和Si分别表示通过堆叠i（i = 1，...，I）传输到衬底中的实际和目标能量通量。 这些堆叠暴露于由所计算的Pj（j = 1，...，J）表征的源的辐射。
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公开(公告)号：US20100044592A1
公开(公告)日：2010-02-25
申请号：US12610630
申请日：2009-11-02
CPC分类号： B23K26/0626 , B23K26/0608 , H01L21/26513 , H01L21/2686
摘要： A system for configuring and utilizing J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≧I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |VI−SI| is about minimized with respect to Pi (i=1, . . . , I).
摘要翻译： 一种用于配置和利用J电磁辐射源（J≥2）以串行照射衬底的系统。 每个源具有不同的发射辐射的波长和角分布的功能。 基板包括基层和I堆叠（I≥2;J≥I）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 在I独立暴露步骤中，I堆叠同时暴露于来自J源的辐射。 Vi和Si分别表示在曝光步骤i（i = 1，...，I）中通过堆叠i传输到衬底中的实际和目标能量通量。 计算t（i）和Pt（i），使得：与部署i = 1的任何其他源相比，通过部署源t（i），Vi最大。 。 。 ， 一世; 并且误差E是| V1-S1 |，| V2-S2 |的函数。 。 。 ，| VI-SI | 相对于Pi（i = 1，...，I）被最小化。
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公开(公告)号：US07473593B2
公开(公告)日：2009-01-06
申请号：US11275514
申请日：2006-01-11
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.
摘要翻译： 用于形成具有扩大的栅极顶部的半导体晶体管的方法通过在晶体管的栅电极区域的顶部中注入原子来扩展栅极。 所形成的晶体管包括具有两个源极/漏极区域和形成在源极/漏极区域之间的沟道区域上的栅极电介质区域的半导体区域。 栅极区域形成在栅极电介质区域上。 栅电极区域形成为通过栅极电介质区域与沟道区域电绝缘。 所形成的栅极电极区域的顶部比栅电极区域的底部宽。
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公开(公告)号：US20080213964A1
公开(公告)日：2008-09-04
申请号：US12037113
申请日：2008-02-26
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
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