公开(公告)号：US20080157188A1

公开(公告)日：2008-07-03

申请号：US12037121

申请日：2008-02-26

申请人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

IPC分类号： H01L29/00

CPC分类号： H01L29/42384 ,  H01L29/66772 ,  H01L29/78654

摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与 所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度 厚度。

公开(公告)号：US20080213964A1

公开(公告)日：2008-09-04

申请号：US12037113

申请日：2008-02-26

申请人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/66772 ,  H01L29/78654

摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

公开(公告)号：US20080142806A1

公开(公告)日：2008-06-19

申请号：US11610533

申请日：2006-12-14

申请人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795

摘要： A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel region and electrically isolated from the channel region by a first gate dielectric layer; and a FinFET formed in single crystal silicon block on top of and electrically isolated from the substrate, the FinFET comprising a second channel region, third and fourth source drains on opposite first and second ends of a second channel region and the gate, the gate electrically isolated from the second channel region by a second gate dielectric layer.

摘要翻译： 半导体器件。 该器件包括：形成在单晶硅衬底中的平面FET，所述FET包括第一沟道区，在第一沟道区的相对侧上的第一和第二源极漏极和栅极，沟道区上方的栅极和电隔离 从所述沟道区域通过第一栅极介电层; 以及在衬底顶部并与电极隔离的单晶硅块中形成的FinFET，所述FinFET包括第二沟道区，第三和第四源在第二沟道区的相对的第一和第二端上漏极，栅极电 通过第二栅极介电层与第二沟道区隔离。

公开(公告)号：US20080090367A1

公开(公告)日：2008-04-17

申请号：US11549311

申请日：2006-10-13

申请人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Andres Bryant ,  William F. Clark ,  Edward Joseph Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/66772 ,  H01L29/78654

摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

公开(公告)号：US5959335A

公开(公告)日：1999-09-28

申请号：US159307

申请日：1998-09-23

申请人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

发明人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7841 ,  H01L27/1203

摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

公开(公告)号：US06249029B1

公开(公告)日：2001-06-19

申请号：US09320595

申请日：1999-05-26

申请人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

发明人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

IPC分类号： H01L2976

CPC分类号： H01L29/7841 ,  H01L27/1203

摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

公开(公告)号：US20080217707A1

公开(公告)日：2008-09-11

申请号：US11683470

申请日：2007-03-08

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78615 ,  H01L29/783

摘要： A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body.

摘要翻译： 公开了一种具有直接接触门和体的晶体管及相关方法。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。 一种方法可以包括提供身体; 形成与身体的侧壁的至少一部分接触的牺牲层; 在所述至少一部分之外形成围绕所述主体的介电层; 去除牺牲层; 以及围绕所述主体形成所述门，使得所述门接触所述主体的侧壁的至少一部分。

公开(公告)号：US20080122010A1

公开(公告)日：2008-05-29

申请号：US11555826

申请日：2006-11-02

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： A transistor and related method are disclosed. The transistor may include a gate, a sidewall spacer formed along the gate, and a source/drain region positioned only under the sidewall spacer except for a portion at which a contact is positioned. The transistor may be ultra-low power and sub-threshold voltage or near sub-threshold voltage. The transistor may exhibit at least two times reduction in outer fringe capacitance (Cof).

摘要翻译： 公开了一种晶体管及相关方法。 晶体管可以包括栅极，沿着栅极形成的侧壁隔离物，以及仅位于侧壁隔板之下的源极/漏极区域，除了接触位置的部分之外。 晶体管可能是超低功耗和次阈值电压或接近亚阈值电压。 晶体管可以表现出外边缘电容（C SUB）的至少两倍的降低。

公开(公告)号：US4353478A

公开(公告)日：1982-10-12

申请号：US242227

申请日：1981-03-10

申请人： William F. Clark

发明人： William F. Clark

IPC分类号： B65D88/46 ,  B65D88/50

CPC分类号： B65D88/46

摘要： In a storage tank for liquids, such as petroleum liquids and the like of the type having a generally upstanding cylindrical tank wall and disposed within the wall a generally circular roof therefor adapted to float upon the contents of the tank in vertically movable relation according to a variation in the volume of such contents so as to define a clearance space being defined between the inner wall surface and the outer peripheral rim of said floating roof, an improved vapor seal for said clearance space comprising an elongated resilient pad extending circularly around the inner face of the tank wall with its long axis in generally upstanding relation to the tank top and its outer face at least partially in contact with the wall, such pad having an exterior surface constituted of durable material resistant to attack by the liquid being stored and being supported by a plurality of supports arranged at spaced points around said roof rim, each such support having a base section affixed to the roof rim, a substantially rigid arm hingedly connected at its lower end to the base section and extending generally upwardly therefrom, an extension at the upper end of the arm in engagement with the inner face of the pad, and means for biasing the arm outwardly from said base to urge the outer face of the pad against the tank inner wall; and a circular skirt of flexible impervious material substantially sealed along its top and bottom edges respectively to the lower end of the pad and the tank rim and spanning therebetween.

摘要翻译： 在用于液体的储罐中，例如具有大体上直立的圆柱形罐壁的石油液体等，并且设置在壁内，大致圆形的屋顶适于根据垂直方向的浮动关系漂浮在罐的内容物上 这样的内容物的体积变化以便限定在所述浮动屋顶的内壁表面和外周边缘之间限定的间隙空间，用于所述间隙空间的改进的蒸气密封件包括细长的弹性垫，该弹性垫围绕内表面圆周地延伸 罐壁的长轴与罐顶部和其外表面至少部分地与壁接触，其外表面具有外表面，该外表面由耐受材料冲击的耐久材料构成，并被支撑 通过布置在围绕所述屋顶边缘的间隔开的点处的多个支撑件，每个这样的支撑件具有固定在t上的基部 在屋顶边缘处，基本上刚性的臂在其下端处铰接地连接到基部并且大体向上延伸，在臂的上端处与垫的内表面接合的延伸部，以及用于偏置臂的装置 从所述基座向外推动所述垫的外表面抵靠所述罐内壁; 以及柔性不透水材料的圆形裙部，其基本上沿其顶部和底部边缘分别密封到垫和罐边缘的下端并跨越其间。

公开(公告)号：US20080265343A1

公开(公告)日：2008-10-30

申请号：US11740442

申请日：2007-04-26

申请人： Brian J. Greene ,  William F. Clark ,  Bruce B. Doris

发明人： Brian J. Greene ,  William F. Clark ,  Bruce B. Doris

IPC分类号： H01L29/772

CPC分类号： H01L21/28114 ,  H01L21/28026 ,  H01L21/28079 ,  H01L29/49 ,  H01L29/495 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance.

摘要翻译： 半导体结构包括位于半导体衬底内分离多个源极和漏极区域的沟道区域上方的反向T形栅电极。 倒置的T形栅电极可以在其水平部分和其垂直部分中包括不同的栅电极材料。 半导体结构可以用层间电介质（ILD）层钝化，通过该层可以定位并形成与多个源区和漏区接触的多个通孔。 由于倒置的T形栅电极，半导体结构表现出减小的栅电极到通孔电容。