公开(公告)号：US06717832B2

公开(公告)日：2004-04-06

申请号：US10208444

申请日：2002-07-29

申请人： Bret Johnson ,  Aaron Nygren

发明人： Bret Johnson ,  Aaron Nygren

IPC分类号： G11C502

CPC分类号： G11C7/1072 ,  G11C7/10 ,  G11C11/4093 ,  G11C2207/105

摘要： A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

摘要翻译： 描述了一种通信方法，其中两个存储器模块经由公共数据和命令总线从控制器模块接收数据和命令。 内存模块包含有效的线路终端。 通过第二芯片选择输入，其中一个存储器模块可以监视从控制器模块传递到另一个存储器模块的写入命令，从而激活监视存储器模块中的线路终端。

公开(公告)号：US20070244930A1

公开(公告)日：2007-10-18

申请号：US11695265

申请日：2007-04-02

申请人： Troy Bartlette ,  Bernard Henry ,  Said Mohammadioun ,  David McDonald ,  William Jones ,  Bret Johnson

发明人： Troy Bartlette ,  Bernard Henry ,  Said Mohammadioun ,  David McDonald ,  William Jones ,  Bret Johnson

IPC分类号： G06F7/00

CPC分类号： G06F9/44505

摘要： The present invention provides a system and method for utilizing profile information to set and maintain general and applications settings. In architecture, the system includes a computer device for performing the operation. The computer device comprises an operation module that determines an operation type and a setting module that determines the set of setting to perform the operation on the computer device. Moreover, the computer device further comprises an acquisition module that acquires the set of setting to perform the operation on the computer device. The present invention can also be viewed as a method for utilizing profile information to set and maintain general and applications settings. The method operates by (1) determining the operation on the computer device; (2) determining the set of setting to perform the operation on the computer device; and (3) acquiring the set of setting to perform the operation on the computer device.

摘要翻译： 本发明提供一种利用简档信息来设置和维护一般和应用设置的系统和方法。 在架构中，该系统包括用于执行操作的计算机设备。 计算机设备包括确定操作类型的操作模块和确定在计算机设备上执行操作的一组设置的设置模块。 此外，计算机装置还包括获取模块，其获取在计算机设备上执行操作的一组设置。 本发明还可以被视为利用简档信息来设置和维护一般和应用设置的方法。 该方法通过以下步骤操作：（1）确定计算机设备上的操作; （2）确定在计算机设备上执行操作的设置集合; 和（3）获取在计算机设备上执行操作的设置集合。

公开(公告)号：US06246264B1

公开(公告)日：2001-06-12

申请号：US09408689

申请日：1999-09-30

申请人： Bret Johnson

发明人： Bret Johnson

IPC分类号： H03K19003

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22

摘要： An output driver circuit of a clocked integrated semiconductor memory of the DRAM type is driven by a circuit for generating an output signal as a function of two input signals. A validity signal, which is supplied to the circuit, ensures that the data to be output are in a valid state before the output driver is activated. As a result, a situation in which different propagation times of input signals of the output driver circuit lead to multiple switching operations within an access cycle of a memory access is prevented. An event-oriented control of the enabling process of the output driver ensures a proper function even in the case of variable frequencies of the clock control.

摘要翻译： DRAM类型的时钟集成半导体存储器的输出驱动器电路由用于产生作为两个输入信号的函数的输出信号的电路驱动。 提供给电路的有效信号确保在输出驱动器被激活之前要输出的数据处于有效状态。 结果，防止输出驱动电路的输入信号的不同传播时间在存储器访问的访问周期内导致多次切换操作的情况。 即使在时钟控制的可变频率的情况下，输出驱动器的使能过程的面向事件的控制确保了适当的功能。

公开(公告)号：US06304491B2

公开(公告)日：2001-10-16

申请号：US09776950

申请日：2001-02-05

申请人： Bret Johnson ,  Robert Kaiser

发明人： Bret Johnson ,  Robert Kaiser

IPC分类号： G11C700

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12

摘要： An integrated semiconductor memory having memory cells (MC) for storing data signals (DQ), has a memory sense amplifier (2) with an input (21) for a data signal (DQ) of one of the memory cells (MC), and an output (23) for at least one output signal (RD0). A driver circuit (3) is connected to the output (23) of the memory sense amplifier (2). The driver circuit (3) can be activated or deactivated only by the output signal (RD0) of the memory sense amplifier (2). A signal line (4) is connected to the driver circuit (3), a precharging circuit (5) and to a memory circuit (6). A terminal (7) for a control signal (C) is connected to the memory sense amplifier (2), the precharging circuit (5) and the memory circuit (6). As result of a driver circuit (3) which has a relatively low level of circuit complexity, the space requirements are kept relatively small. In addition, high switching speeds are made possible during the reading operation.

公开(公告)号：US06208562B1

公开(公告)日：2001-03-27

申请号：US09536029

申请日：2000-03-27

申请人： Martin Zibert ,  Bret Johnson

发明人： Martin Zibert ,  Bret Johnson

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： The digital memory has at least one data line and address lines. It also has a switching unit that, in an active state, inverts signals on the data line or on at least one of the address lines and that, in an inactive state, leaves the signals unchanged. In a first operating mode, the switching unit is in the same state for writing and reading. In a second operating mode, the switching unit is in respectively opposite states for writing and for reading.

摘要翻译： 数字存储器具有至少一条数据线和地址线。 它还具有开关单元，其处于活动状态，使数据线上或至少一个地址线上的信号反相，并且在非活动状态下使信号保持不变。 在第一操作模式中，切换单元处于用于写入和读取的相同状态。 在第二操作模式中，切换单元分别处于写入和读取的相反状态。

公开(公告)号：US06198328B1

公开(公告)日：2001-03-06

申请号：US09311120

申请日：1999-05-13

申请人： Patrick Heyne ,  Thoralf Grätz ,  Dieter Härle ,  Bret Johnson

发明人： Patrick Heyne ,  Thoralf Grätz ,  Dieter Härle ,  Bret Johnson

IPC分类号： G06F104

CPC分类号： H03K5/151

摘要： The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

摘要翻译： 电路配置产生互补信号。 输入信号经由第一路径，通过传递元件从输入端子路由到第一输出端子。 输入信号也经由反相器在与第一路径并联连接的第二路径上路由到第二输出端。 第一和第二输出端分别经由补偿装置连接到第一和第二输出节点。 补偿装置补偿第一和第二路径上的信号中的不同时间延迟。

公开(公告)号：US6043691A

公开(公告)日：2000-03-28

申请号：US160862

申请日：1998-09-25

申请人： Bret Johnson ,  Ralf Schneider

发明人： Bret Johnson ,  Ralf Schneider

IPC分类号： H03K5/1252 ,  H03K17/16

CPC分类号： H03K5/1252

摘要： A pulse shaper circuit includes a buffer having an input, an output and two supply connections. A controllable first switch is connected between one of the supply connections and a first supply potential, a controllable second switch is connected between the other supply voltage connection and a second supply potential, a controllable third switch is connected between the output of the buffer and the first supply potential and a controllable fourth switch is connected between the output of the buffer and the second supply potential. A control device for the switches is connected to the output of the buffer and produces a first control pulse of a specific duration at the occurrence of first edges of a signal present at the output of the buffer and a second control pulse of a specific duration at the occurrence of second edges. The first control pulse changes over the first switch from the ON state to the OFF state and the fourth switch from the OFF state to the ON state. The second control pulse changes over the second switch from the ON state to the OFF state and the third switch from the OFF state to the ON state.

摘要翻译： 脉冲整形器电路包括具有输入，输出和两个电源连接的缓冲器。 一个可控的第一开关连接在一个电源连接点和一个第一电源电位之间，一个可控的第二开关连接在另一个电源电压连接和第二个电源电位之间，可控制的第三个开关连接在缓冲器的输出端和 第一供电电位和可控第四开关连接在缓冲器的输出端与第二供电电位之间。 用于开关的控制装置连接到缓冲器的输出，并且在存在于缓冲器的输出处的信号的第一边缘出现特定持续时间的第一控制脉冲和特定持续时间的第二控制脉冲 发生第二个边缘。 第一控制脉冲从第一开关从接通状态切换到断开状态，第四开关从断开状态转换到接通状态。 第二控制脉冲将第二开关从ON状态切换到OFF状态，将第三开关从OFF状态切换到ON状态。

公开(公告)号：US5994936A

公开(公告)日：1999-11-30

申请号：US160880

申请日：1998-09-25

申请人： Bret Johnson ,  Ralf Schneider

发明人： Bret Johnson ,  Ralf Schneider

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356113 ,  H03K3/037 ,  H03K3/356165

摘要： An RS flip-flop has an inverter, connected to an input terminal of the RS flip-flop, a NOR gate having an Enable-Set input, a NAND gate having an Enable-Reset input, and a first and a second transistor connected to the inverter. The outputs of the NOR and NAND gates are connected, via the gate paths of the first and second transistors, to the gate electrode of a third and a fourth transistor, respectively. The third and the fourth transistor are connected in series and form a holding element, whose common connection point is connected to the output of the inverter and to the output terminal of the flip-flop.

摘要翻译： RS触发器具有连接到RS触发器的输入端的反相器，具有使能置位输入的或非门，具有使能复位输入的与非门和与第一和第二晶体管连接的 逆变器。 NOR和NAND门的输出分别经由第一和第二晶体管的栅极连接到第三和第四晶体管的栅电极。 第三和第四晶体管串联连接并形成保持元件，其公共连接点连接到反相器的输出端和触发器的输出端。

公开(公告)号：US06756820B1

公开(公告)日：2004-06-29

申请号：US09311118

申请日：1999-05-13

申请人： Patrick Heyne ,  Thoralf Grätz ,  Dieter Härle ,  Bret Johnson

发明人： Patrick Heyne ,  Thoralf Grätz ,  Dieter Härle ,  Bret Johnson

IPC分类号： H03K1920

CPC分类号： H03K17/693

摘要： The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

摘要翻译： 所述优化延迟多路复用器包括至少两个通过元件，所述至少两个通过元件分别通过控制信号经由第一路径被驱动，并且经由第二路径被由逆变器反相的控制信号。 在第一路径中连接另外的通过元件以模拟由逆变器引起的延迟。 结果，同时切换至少两个通过元件。

公开(公告)号：US06487127B2

公开(公告)日：2002-11-26

申请号：US09906451

申请日：2001-07-16

申请人： Bret Johnson ,  Eckhard Plättner ,  Helmut Schneider

发明人： Bret Johnson ,  Eckhard Plättner ,  Helmut Schneider

IPC分类号： G11C1604

CPC分类号： G11C7/1048 ,  G11C7/065 ,  G11C11/4091

摘要： Binary information is written to and read from a memory cell field forming a matrix-type field of rows and columns via a plurality of write/read circuits, each having a latch flipflop with at least one data terminal connected on one side to an allocated column-related bit line and on the other side, by way of a gate circuit, to a data line. Access to the relevant bit line is accomplished via a column selection signal which controls the gate circuit. A switching device facilitates the writing process. After the excitation of any row-related word line, the switching device interrupts the current supply of the latch flipflops that are selected for an access starting no earlier than when the relevant latch flipflop assumes a state indicating the information content of the accessed memory cell and, at the latest, during the active interval of the relevant column selection signal.