Method and apparatus to drive a linear resonant actuator at its resonant frequency
    1.
    发明授权
    Method and apparatus to drive a linear resonant actuator at its resonant frequency 有权
    在其谐振频率下驱动线性谐振致动器的方法和装置

    公开(公告)号:US09054627B2

    公开(公告)日:2015-06-09

    申请号:US13443741

    申请日:2012-04-10

    摘要: A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.

    摘要翻译: 提供了一种用于驱动线性谐振致动器(LRA)的方法。 在第一个关闭间隔期间,测量LRA的反电动势。 在第一关闭间隔期间,当反电动势达到预定阈值时,启动定时器,并且在第一关闭间隔期间在反电动势达到预定阈值之后经过预定延迟之后,LRA在驱动间隔 具有长度和驱动力。 在驱动间隔之后输入第二个关闭间隔,并且在第二个关闭间隔期间,测量LRA的反电动势。 在第二关闭间隔期间,当反电动势达到预定阈值时,定时器停止。 对应于在第一关闭间隔期间达到预定阈值的反电动势之间的持续时间的定时器的值和在第二关闭间隔期间达到预定阈值的反电动势确定长度。

    Single supply class-D amplifier
    3.
    发明授权
    Single supply class-D amplifier 有权
    单电源D类放大器

    公开(公告)号:US08008969B1

    公开(公告)日:2011-08-30

    申请号:US12750494

    申请日:2010-03-30

    IPC分类号: H03F3/38

    摘要: Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in efficiency, and oftentimes included separate power management circuits. Here, a class-D amplifier is provided with an output stage that provides negative supply voltages, positive supply voltages, and ground. Essentially, this amplifier provides some of the benefits of the conventional amplifiers without the drawbacks.

    摘要翻译: 传统上,具有负电源轨的开关放大器(即D类和G类)具有直流(DC)功率损耗的问题,包括大的外部电容器,效率相对降低,并且通常包括单独的功率管理电路。 这里,D类放大器具有提供负电源电压,正电源电压和接地的输出级。 本质上,该放大器提供了常规放大器的一些优点,而没有缺点。

    Combination trim and CMFB circuit and method for differential amplifiers
    4.
    发明授权
    Combination trim and CMFB circuit and method for differential amplifiers 有权
    差分放大器的组合调整和CMFB电路及方法

    公开(公告)号:US07733179B2

    公开(公告)日:2010-06-08

    申请号:US12288481

    申请日:2008-10-21

    申请人: Brett E. Forejt

    发明人: Brett E. Forejt

    IPC分类号: H03F3/45

    摘要: A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first (12) and second (13) conductors to the first and second load devices, respectively. Common mode feedback circuitry (6A) including first (M3), second (M4), and third (M5) transistors is combined with offset correction circuitry (8) including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (11). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (VOCM) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

    摘要翻译: 差分放大器(10-1,2)包括包括第一(M1)和第二(M2)输入晶体管和第一(4A)和第二(4B)负载装置的输入级(7)。 第一和第二输入晶体管的源极连接在一起。 第一和第二输入晶体管的漏极分别由第一(12)和第二(13)导体耦合到第一和第二负载装置。 包括第一(M3),第二(M4)和第三(M5)晶体管的共模反馈电路(6A)与包括第二晶体管和第三晶体管的偏移校正电路(8)组合。 第一,第二和第三晶体管的源极耦合到尾电流源(11)。 第二和第三晶体管的漏极分别耦合到第一和第二导体。 共模电压(VOCM)被施加到第一晶体管的栅极。 偏移调整电压施加到第二和第三晶体管的栅极。

    Combination trim and CMFB circuit and method for differential amplifiers
    5.
    发明申请
    Combination trim and CMFB circuit and method for differential amplifiers 有权
    差分放大器的组合调整和CMFB电路及方法

    公开(公告)号:US20090108936A1

    公开(公告)日:2009-04-30

    申请号:US12288481

    申请日:2008-10-21

    申请人: Brett E. Forejt

    发明人: Brett E. Forejt

    IPC分类号: H03F3/45

    摘要: A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first (12) and second (13) conductors to the first and second load devices, respectively. Common mode feedback circuitry (6A) including first (M3), second (M4), and third (M5) transistors is combined with offset correction circuitry (8) including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (11). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (VOCM) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

    摘要翻译: 差分放大器(10-1,2)包括包括第一(M1)和第二(M2)输入晶体管和第一(4A)和第二(4B)负载装置的输入级(7)。 第一和第二输入晶体管的源极连接在一起。 第一和第二输入晶体管的漏极分别由第一(12)和第二(13)导体耦合到第一和第二负载装置。 包括第一(M3),第二(M4)和第三(M5)晶体管的共模反馈电路(6A)与包括第二晶体管和第三晶体管的偏移校正电路(8)组合。 第一,第二和第三晶体管的源极耦合到尾电流源(11)。 第二和第三晶体管的漏极分别耦合到第一和第二导体。 共模电压(VOCM)被施加到第一晶体管的栅极。 偏移调整电压施加到第二和第三晶体管的栅极。

    Capacitor compensation in miller compensated circuits
    6.
    发明授权
    Capacitor compensation in miller compensated circuits 有权
    磨机补偿电路中的电容补偿

    公开(公告)号:US06788146B2

    公开(公告)日:2004-09-07

    申请号:US10320123

    申请日:2002-12-16

    IPC分类号: H03F345

    摘要: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

    摘要翻译: 米勒补偿放大器电路。 该电路包括放大器级和与放大器级并联布置的补偿电容器。 电流乘法器电路路径,其适于使通过补偿电容器的电流相乘包括在当前乘法器电路路径中的反相级。 反相级包括第一电流镜,其适于镜像对应于通过补偿电容器的电流的第一电流,以提供第二电流,以及适于镜像和反转第二电流以提供第三电流的第二电流镜,以及 以将第三电流施加到放大器级。 以这种方式,电路是仅由单个电容器进行的米勒补偿,其电容根据电流模式乘法相乘。

    Sigma delta class D architecture which corrects for power supply, load and H-bridge errors
    7.
    发明授权
    Sigma delta class D architecture which corrects for power supply, load and H-bridge errors 有权
    Sigma delta D类架构,用于纠正电源,负载和H桥错误

    公开(公告)号:US06943717B1

    公开(公告)日:2005-09-13

    申请号:US10955113

    申请日:2004-09-30

    申请人: Brett E. Forejt

    发明人: Brett E. Forejt

    IPC分类号: H03M3/00

    摘要: A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value includes: a first summing node having a positive input coupled to a signal input node; a second summing node having a first positive input coupled to an output of the first summing node and having an output coupled to a signal output node; a low pass filter having an input coupled to the output of the second summing node; an analog to digital converter having an input coupled to an output of the low pass filter; a third summing node having a positive input node coupled to an output of the analog to digital converter and a negative input node coupled to the output of the first summing node; and a feedback device coupled between an output of the third summing node and a negative input of the first summing node.

    摘要翻译: 使用低通滤波器平滑输出波形并从反馈值消除高频开关噪声的Σ-Δ类D装置包括:具有耦合到信号输入节点的正输入的第一求和节点; 第二求和节点,其具有耦合到所述第一求和节点的输出并且具有耦合到信号输出节点的输出的第一正输入; 低通滤波器,具有耦合到第二求和节点的输出的输入; 具有耦合到低通滤波器的输出的输入的模数转换器; 具有耦合到所述模数转换器的输出的正输入节点和耦合到所述第一求和节点的输出的负输入节点的第三求和节点; 以及耦合在第三求和节点的输出和第一求和节点的负输入之间的反馈设备。

    High output swing comparator stage
    8.
    发明授权
    High output swing comparator stage 有权
    高输出摆幅比较器级

    公开(公告)号:US06617921B2

    公开(公告)日:2003-09-09

    申请号:US09988474

    申请日:2001-11-20

    申请人: Brett E. Forejt

    发明人: Brett E. Forejt

    IPC分类号: H03F345

    摘要: A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.

    摘要翻译: 提供了一种电路和方法,其向与晶体管跨导匹配的比较器器件提供放大级,以提供足够的放大,并采用二极管耦合晶体管来控制共模输出偏置电压。 该电路和方法提供了具有对输出共模电压的控制的高增益比较器级,同时在差分模式下提供轨至轨输出摆幅,而不向比较器装置提供外部反馈。