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公开(公告)号：US06870398B2
公开(公告)日：2005-03-22
申请号：US10422137
申请日：2003-04-24
摘要： Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.
摘要翻译： 公开了用于在执行在集成电路上执行逻辑功能（或需要密集互连结构的其它类型的功能）的电路的一个或多个区域内分配存储器的系统和方法。 分布式存储器降低了高密度路由拥塞，允许增加逻辑利用率，并为附加互连结构提供区域。 还公开了用于访问存储器的各种技术。
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公开(公告)号：US06816401B2
公开(公告)日：2004-11-09
申请号：US10406526
申请日：2003-04-03
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.
摘要翻译： SRAM存储器包括耦合到SRAM单元阵列中的每行字线的上拉器件。 上拉装置的尺寸使得当选择行时，关联字线完全充电的时间足够慢，使得存储在所选择的SRAM单元中的数据在读取操作期间不被破坏。 通过对字线进行缓慢充电，相应的存取晶体管也缓慢导通，导致耦合位线从存储在SRAM单元中的数据缓慢充电或放电。 由于存储数据和耦合位线之间没有突然的大电荷转移，所以在读取操作期间数据不会被破坏，并且不需要读取预充电电路。
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公开(公告)号：US07804350B1
公开(公告)日：2010-09-28
申请号：US12428285
申请日：2009-04-22
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A level-shifter circuit capable of operating at low voltages. Two complementary current paths are provided between each of two intermediate nodes (at least one of which being an output node) and one of the supply voltages. A network of field-effect transistors are coupled between the other voltage supply and the intermediate nodes. The transistors include a pull-up (or pull-down as the case may be) transistor pair coupled to the high (or low as the case may be) voltage supply. There are two cascode transistor pairs coupled between the pull-up (or down) transistors and the corresponding intermediate node. One cascode pair couples the respective intermediate node to the drain terminal of the respective pull-up (or down) transistor. The other cascoded pair cross-couples the intermediate node to the gate terminal of the opposite pull-up (or down) transistor.
摘要翻译： 能够在低电压下工作的电平转换电路。 在两个中间节点（其中至少一个是输出节点）和电源电压之一之间的每一个之间提供两个互补电流路径。 场效应晶体管的网络耦合在另一电压源和中间节点之间。 晶体管包括耦合到高电压（或尽可能低的情况）的电压供应的上拉（或下拉，视情况而定）晶体管对。 耦合在上拉（或下降）晶体管和相应的中间节点之间的两个共源共栅晶体管对。 一个共源共栅对将相应的中间节点耦合到相应的上拉（或向下）晶体管的漏极端子。 另一个串联对将中间节点交叉耦合到相反上拉（或下降）晶体管的栅极端子。
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公开(公告)号：US5521556A
公开(公告)日：1996-05-28
申请号：US379049
申请日：1995-01-27
CPC分类号： H03K3/0315 , H03L7/097 , H03L7/181
摘要： A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator. The frequency converter has a highly linear transfer function which is established by the resolution of a frequency counter. For example, a transfer function having approximately 0.1% accuracy in linearity is achieved using a 10-bit resolution frequency counter. Using indirect frequency synthesis, the controlled oscillator generates precisely controlled timing signals.
摘要翻译： 使用反馈控制回路的单片变频器基于诸如晶体振荡器或外部频率源的定时源在宽动态范围上产生合成频率信号源。 变频器包括受控振荡器，频率计数器，定时信号发生器，并连接在频率计数器和受控振荡器之间，数模转换器和差分积分器。 受控振荡器以由电信号控制的频率产生时钟信号。 差分积分器连接到输入信号端并连接到定时信号发生器。 差分积分器确定输入信号和由数模转换器操作的信号之间的差分信号，并在由定时信号发生器产生的定时信号的控制下对差分信号进行积分。 变频器具有通过频率计数器的分辨率建立的高度线性传递函数。 例如，使用10位分辨率频率计数器实现线性精度约为0.1％的传递函数。 使用间接频率合成，受控振荡器产生精确控制的定时信号。
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