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公开(公告)号：US06870398B2
公开(公告)日：2005-03-22
申请号：US10422137
申请日：2003-04-24
摘要： Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.
摘要翻译： 公开了用于在执行在集成电路上执行逻辑功能（或需要密集互连结构的其它类型的功能）的电路的一个或多个区域内分配存储器的系统和方法。 分布式存储器降低了高密度路由拥塞，允许增加逻辑利用率，并为附加互连结构提供区域。 还公开了用于访问存储器的各种技术。
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公开(公告)号：US06816401B2
公开(公告)日：2004-11-09
申请号：US10406526
申请日：2003-04-03
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.
摘要翻译： SRAM存储器包括耦合到SRAM单元阵列中的每行字线的上拉器件。 上拉装置的尺寸使得当选择行时，关联字线完全充电的时间足够慢，使得存储在所选择的SRAM单元中的数据在读取操作期间不被破坏。 通过对字线进行缓慢充电，相应的存取晶体管也缓慢导通，导致耦合位线从存储在SRAM单元中的数据缓慢充电或放电。 由于存储数据和耦合位线之间没有突然的大电荷转移，所以在读取操作期间数据不会被破坏，并且不需要读取预充电电路。
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公开(公告)号：US06437616B1
公开(公告)日：2002-08-20
申请号：US09741317
申请日：2000-12-19
IPC分类号： H03L706
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/0818 , H03L7/095 , H03L7/10 , H03L2207/14 , Y10S331/02
摘要： A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block. The delay lock loop circuit is capable of handling a wide range of clock frequencies and a step increase or decrease in the clock frequency.
摘要翻译： 公开了一种延迟锁定环路电路，其包括延迟块，其接收时钟信号并将时钟信号延迟所选择的量以产生延迟的时钟信号。 相位检测器接收时钟信号和延迟的时钟信号，比较两个信号的相位并产生相位比较信号。 锁定检测器接收时钟信号和延迟的时钟信号，比较两个信号的定时并产生电位锁定指示信号。 控制器接收相位比较信号和电位锁定指示信号，并向延迟块提供延迟控制信号，以响应于相位比较信号改变所选择的延迟量。 响应于潜在的锁定指示信号，控制器以选定的间隔中断对延迟块的时钟信号，并且响应于在延迟块的时钟信号中断之后的电位锁定指示信号，产生真实的锁定指示信号。 延迟锁定环电路能够处理宽范围的时钟频率和时钟频率的逐步增加或减少。
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公开(公告)号：US5170078A
公开(公告)日：1992-12-08
申请号：US601282
申请日：1990-10-22
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/018571
摘要： A highly stable high-voltage output buffer is provided which may be manufactured using standard CMOS technology. As part of the invention, the effects of voltage drift at one or more of the nodes formed between series connected P or N-channel MOSFET devices are generally reduced or eliminated. The present invention includes compensation circuitry which reduces the effects of parasitic coupling within the MOSFET devices, and which serves to compensate for any voltage drift which may occur at the nodes between series connected devices. In addition, the present invention provides a method and apparatus for increasing the current sourcing capability of a CMOS high-voltage output buffer, even under low supply V.sub.vf conditions, without necessarily increasing the size of the output device. Furthermore, the present invention provides a method and apparatus for reducing the effects of coupling along a shared bias line between a plurality of high-voltage output buffers in accordance with the present invention.
摘要翻译： 提供了一种高度稳定的高压输出缓冲器，可以使用标准CMOS技术制造。 作为本发明的一部分，通常减少或消除在串联连接的P或N沟道MOSFET器件之间形成的一个或多个节点处的电压漂移的影响。 本发明包括补偿电路，其减少MOSFET器件内的寄生耦合的影响，并且其用于补偿可能在串联连接的器件之间的节点处发生的任何电压漂移。 此外，本发明提供了即使在低电源Vvf条件下也可以提高CMOS高电压输出缓冲器的电流源能力的方法和装置，而不必增加输出装置的尺寸。 此外，本发明提供一种用于在根据本发明的多个高电压输出缓冲器之间降低沿着共享偏置线的耦合效应的方法和装置。
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公开(公告)号：US5179297A
公开(公告)日：1993-01-12
申请号：US601892
申请日：1990-10-22
CPC分类号： H03K17/102 , G05F3/24
摘要： In a high-voltage output buffer, a self-adjusting bias generator is provided which is capable of automatically adjusting the applied bias voltages in the output buffer so as to enhance the output buffer performance. Under normal or high supply voltage conditions, the bias generator provides a first set of bias voltages to the series-connected transistors in the output buffer. Under low supply voltage conditions, the bias generator provides a second set of bias voltages to the various series-connected transistors.
摘要翻译： 在高压输出缓冲器中，提供了自调整偏压发生器，其能够自动调整输出缓冲器中施加的偏置电压，从而增强输出缓冲器的性能。 在正常或高电源电压条件下，偏置发生器为输出缓冲器中的串联晶体管提供第一组偏置电压。 在低电源电压条件下，偏置发生器为各种串联连接的晶体管提供第二组偏置电压。
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