公开(公告)号：US6128237A

公开(公告)日：2000-10-03

申请号：US455365

申请日：1999-12-06

申请人： Brian Shirley ,  Timothy B. Cowles

发明人： Brian Shirley ,  Timothy B. Cowles

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

摘要翻译： 一种用于降低由与有源字线相关联的多个读出放大器的同时激活而产生的峰值电流的方法和装置，而不会降低半导体存储器件的操作速度。 存储器阵列包括访问存储器单元的字线和跟踪字线，用于通过在每个读出放大器或读出放大器组的激活之后引入延迟并且在激活下一个读出放大器或组之前，顺序激活连接到数字线的读出放大器 的感测放大器，使得与有源字线相关联的所有数字线的感测放大器的激活总时间被扩展，但不超过激活整个字线所需的时间。

公开(公告)号：US6026042A

公开(公告)日：2000-02-15

申请号：US58255

申请日：1998-04-10

申请人： Brian Shirley ,  Timothy B. Cowles

发明人： Brian Shirley ,  Timothy B. Cowles

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

公开(公告)号：US20130003473A1

公开(公告)日：2013-01-03

申请号：US13616704

申请日：2012-09-14

申请人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

发明人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

IPC分类号： G11C7/10

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。 描述其他实施例。

公开(公告)号：US20110209011A1

公开(公告)日：2011-08-25

申请号：US13098569

申请日：2011-05-02

申请人： Christian N. Mohr ,  Timothy B. Cowles

发明人： Christian N. Mohr ,  Timothy B. Cowles

IPC分类号： G06F11/20

CPC分类号： G11C17/18 ,  G11C11/401 ,  G11C29/24 ,  G11C29/44 ,  G11C29/70 ,  G11C29/838 ,  G11C2029/1208 ,  G11C2029/4402

摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

摘要翻译： 在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。 存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。 存储行地址还可以使用分段冗余来指导修复。 作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。 如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

公开(公告)号：US07941712B2

公开(公告)日：2011-05-10

申请号：US11714348

申请日：2007-03-06

申请人： Christian N. Mohr ,  Timothy B. Cowles

发明人： Christian N. Mohr ,  Timothy B. Cowles

IPC分类号： G11C29/00

CPC分类号： G11C17/18 ,  G11C11/401 ,  G11C29/24 ,  G11C29/44 ,  G11C29/70 ,  G11C29/838 ,  G11C2029/1208 ,  G11C2029/4402

摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

摘要翻译： 在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。 存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。 存储行地址还可以使用分段冗余来指导修复。 作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。 如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

公开(公告)号：US20090224242A1

公开(公告)日：2009-09-10

申请号：US12468482

申请日：2009-05-19

申请人： Timothy B. Cowles ,  Aron T. Lunde

发明人： Timothy B. Cowles ,  Aron T. Lunde

IPC分类号： H01L23/00 ,  H01L27/10 ,  H01L21/8232

CPC分类号： G01R31/2884

摘要： An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.

摘要翻译： 一种隔离电路，包括具有栅极的第一晶体管，第一源极/漏极端子和第二源极/漏极端子，耦合到第一晶体管的栅极的第一焊盘，第一焊盘可操作以接收使能信号， 第二焊盘，其耦合到第一晶体管的第一源极/漏极，第二焊盘可操作以接收接地电位;将第二源极/漏极端子耦合到节点的第一熔丝器件;将节点耦合到第一焊盘的第二熔丝器件 第三焊盘，其可操作以接收要施加到至少一个管芯的信号;以及第二晶体管，其可操作以响应于由所述节点提供的控制信号选择性地将在第三焊盘处接收的信号传输到至少一个管芯。

公开(公告)号：US20090085613A1

公开(公告)日：2009-04-02

申请号：US12268782

申请日：2008-11-11

申请人： Timothy B. Cowles ,  Steve Casper

发明人： Timothy B. Cowles ,  Steve Casper

IPC分类号： H03K3/00

CPC分类号： H03K19/018528

摘要： A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.

摘要翻译： 公开了一种低电流输入缓冲器。 缓冲器使用自偏置N和P通道差分对，其输出端连接在一起。 自偏置有助于减少电流消耗。 N沟道和P沟道差分对的组合导致了宽范围的参考电压和电源电压的对称性。

公开(公告)号：US07450450B2

公开(公告)日：2008-11-11

申请号：US11599224

申请日：2006-11-13

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C17/00 ,  G11C11/50 ,  G11C7/10

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C2207/105

摘要： As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the backend of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

摘要翻译： 作为用于存储器件的反熔丝电路的一部分，本发明的优选示例性实施例提供了用于向该抗熔丝提供电压的反熔丝和接触焊盘之间的直接连接。 接触垫还用作存储器件的至少另一部分的电压源。 在存在于焊盘处的电压将损坏电路或使电路不正确地读取反熔丝的状态的情况下，耦合到反熔丝的至少一个电路与其暂时隔离。 接触垫在进程内存储器件的探针级期间可用，但一旦器件被封装，则可以防止接触该接触垫。 在生产过程的后端，反熔丝可以通过第二焊盘访问，第二焊盘与防熔丝的电气连通被调节。

公开(公告)号：US07208758B2

公开(公告)日：2007-04-24

申请号：US10663898

申请日：2003-09-16

申请人： Aron T. Lunde ,  Kevin G. Duesman ,  Timothy B. Cowles

发明人： Aron T. Lunde ,  Kevin G. Duesman ,  Timothy B. Cowles

IPC分类号： H01L23/58

CPC分类号： G11C29/006 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.

摘要翻译： 使用常规处理技术制造其上具有多个骰子的半导体晶片或其它体半导体衬底。 对晶片进行测试以识别功能和非功能性骰子。 功能骰子的位置被分析以确定紧邻或紧密接近的功能骰子的位置。 识别一组功能骰子，并在其间形成互连电路。 然后，一旦互连的功能模具组就从晶片分割，同时保持功能模具组的整体完整性以及芯片之间的相关连接。 还公开了包括一个或多个功能性模组的模块以及制造功能模组和模块的方法。

公开(公告)号：US07206234B2

公开(公告)日：2007-04-17

申请号：US11158243

申请日：2005-06-21

申请人： Dong Pan ,  Timothy B. Cowles

发明人： Dong Pan ,  Timothy B. Cowles

IPC分类号： G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1078

摘要： Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The input buffer operates in a relatively low supply voltage and a relatively wide range of signal levels of the input signals while improving the symmetry between rising and falling signal transitions of the output signal. Other embodiments are described and claimed.

摘要翻译： 本发明的一些实施例包括具有用于接收输入信号以产生输出信号的多个差分放大器的输入缓冲器。 输入缓冲器在输入信号的相对低的电源电压和相对宽的信号电平范围内工作，同时改善输出信号的上升和下降信号转换之间的对称性。 描述和要求保护其他实施例。