公开(公告)号：US20090016477A1

公开(公告)日：2009-01-15

申请号：US11822725

申请日：2007-07-09

申请人： Colin Cramm ,  Shawn Scouten ,  Kenji Suzuki ,  Brian Wall ,  Malcolm Stevens

发明人： Colin Cramm ,  Shawn Scouten ,  Kenji Suzuki ,  Brian Wall ,  Malcolm Stevens

IPC分类号： H03D3/24

CPC分类号： H04L7/0337 ,  H03L7/0812 ,  H03L7/099

摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.

摘要翻译： 公开了信号定时相位选择和定时获取装置和技术。 从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。 所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。 每个定时相位可以对接收到的信号进行一次或多次采样。 在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

公开(公告)号：US07308060B1

公开(公告)日：2007-12-11

申请号：US10373301

申请日：2003-02-26

申请人： Brian Wall ,  Shawn Scouten ,  Kenji Suzuki ,  Malcolm Stevens

发明人： Brian Wall ,  Shawn Scouten ,  Kenji Suzuki ,  Malcolm Stevens

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/081 ,  H03L7/18

摘要： An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.

摘要翻译： 提供一种开眼器电路，其在被抖动破坏之后对数据信号执行数据重新定时/眼睛打开功能。 该电路使用由时钟源驱动的PLL，该时钟源是与原始数据信号定时相同的时钟源。 PLL产生用于重新定时数据的本地时钟。 相位误差可能被引入PLL或数据信号。

公开(公告)号：US07519750B2

公开(公告)日：2009-04-14

申请号：US11488124

申请日：2006-07-18

申请人： Shawn Scouten ,  Colin Cramm ,  Malcolm Stevens ,  Kenji Suzuki ,  Brian Wall ,  Med Belhadj

发明人： Shawn Scouten ,  Colin Cramm ,  Malcolm Stevens ,  Kenji Suzuki ,  Brian Wall ,  Med Belhadj

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F12/00 ,  H03L7/06 ,  H03K5/01

CPC分类号： H04L7/10 ,  H03L7/0807 ,  H03L7/087 ,  H04L7/033 ,  H04L2007/047

摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

摘要翻译： 本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从 订户数据突发。 该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。 在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。 本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

公开(公告)号：US20080022143A1

公开(公告)日：2008-01-24

申请号：US11488124

申请日：2006-07-18

申请人： Shawn Scouten ,  Colin Cramm ,  Malcolm Stevens ,  Kenji Suzuki ,  Brian Wall ,  Med Belhadj

发明人： Shawn Scouten ,  Colin Cramm ,  Malcolm Stevens ,  Kenji Suzuki ,  Brian Wall ,  Med Belhadj

IPC分类号： G06F1/12

CPC分类号： H04L7/10 ,  H03L7/0807 ,  H03L7/087 ,  H04L7/033 ,  H04L2007/047

摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.

摘要翻译： 本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从 订户数据突发。 该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。 在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。 本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

公开(公告)号：US07848474B2

公开(公告)日：2010-12-07

申请号：US11822725

申请日：2007-07-09

申请人： Colin Cramm ,  Shawn Scouten ,  Kenji Suzuki ,  Brian Wall ,  Malcolm Stevens

发明人： Colin Cramm ,  Shawn Scouten ,  Kenji Suzuki ,  Brian Wall ,  Malcolm Stevens

IPC分类号： H03D3/24

CPC分类号： H04L7/0337 ,  H03L7/0812 ,  H03L7/099

摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.

摘要翻译： 公开了信号定时相位选择和定时获取装置和技术。 从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。 所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。 每个定时相位可以对接收到的信号进行一次或多次采样。 在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

公开(公告)号：US08384452B1

公开(公告)日：2013-02-26

申请号：US13231798

申请日：2011-09-13

申请人： Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

发明人： Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  H03L7/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

摘要翻译： 数字检测参考时钟信号和反馈信号之间的相位差。 合成相位检测信号被数字滤波，并且在数字滤波相位检测信号的控制下，在分数合成器中合成PLL（锁相环）输出信号。 可以包括整数分频器和/或分数N分频器的反馈路径基于PLL输出信号提供反馈信号。 宽带分数合成器和低带宽数字PLL的组合提供了具有宽带宽PLL的低带宽抖动滤波功能，以抑制VCO（压控振荡器）噪声和串扰。

公开(公告)号：US08390358B2

公开(公告)日：2013-03-05

申请号：US12900424

申请日：2010-10-07

申请人： Shawn Scouten ,  Malcolm Stevens ,  Kevin Parker

发明人： Shawn Scouten ,  Malcolm Stevens ,  Kevin Parker

IPC分类号： H03K3/00

CPC分类号： H03L7/23

摘要： Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.

摘要翻译： 提供了兼容抖动的时钟信号发生装置和方法。 使用具有不同频率的输入信号来产生具有紧密间隔的频率的各个时钟信号。 输入信号可以例如在接收参考时钟信号的相邻锁相环（PLL）中产生。 参考时钟信号或参考时钟信号源自其的信号也是紧密间隔的。 紧密间隔的参考时钟信号被有效地分离以进行清理，然后返回到一起以提供紧密间隔的时钟信号。 这允许清除紧密间隔的参考时钟信号以交错和更广泛间隔的频率发生。 这些技术也可以应用于与谐波相关并用于产生谐波相关的输出时钟信号的参考时钟信号。

公开(公告)号：US20120086491A1

公开(公告)日：2012-04-12

申请号：US12900424

申请日：2010-10-07

申请人： Shawn Scouten ,  Malcolm Stevens ,  Kevin Parker

发明人： Shawn Scouten ,  Malcolm Stevens ,  Kevin Parker

IPC分类号： H03K3/00

CPC分类号： H03L7/23

摘要： Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.

摘要翻译： 提供了兼容抖动的时钟信号发生装置和方法。 使用具有不同频率的输入信号来产生具有紧密间隔的频率的各个时钟信号。 输入信号可以例如在接收参考时钟信号的相邻锁相环（PLL）中产生。 参考时钟信号或参考时钟信号源自其的信号也是紧密间隔的。 紧密间隔的参考时钟信号被有效地分离以进行清理，然后返回到一起以提供紧密间隔的时钟信号。 这允许清除紧密间隔的参考时钟信号以交错和更广泛间隔的频率发生。 这些技术也可以应用于与谐波相关并用于产生谐波相关的输出时钟信号的参考时钟信号。