-
1.发明申请公开(公告)号：US20220408047A1
公开(公告)日：2022-12-22
申请号：US17842279
申请日：2022-06-16
发明人： Shunsuke OKURA , Ai OTANI , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N5/378 , H04N5/355 , H04N5/363 , H04N5/3745
摘要： Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus capable of reading signals produced with different conversion gains and having different signal directions.
A pixel signal processing part 400 includes a first reading part 410 and a second reading part 420. Of a pixel signal PIXOUT input into an input node ND401, the first reading part 410 inverts the signal direction of a first-conversion-gain signal (HCGRST, HCGSIG) and outputs an inverted first-conversion-gain signal (HCGRST, HCGSIG), which has been subjected to inversion and amplification, to an AD converting part 430 via a connection node ND402. Of the pixel signal PIXOUT input into the input node ND401, the second reading part 420 keeps the signal direction of a second-conversion-gain signal (LCGSIG, LCGRST) unchanged, and outputs a non-inverted second-conversion-gain signal (LCGSIG, LCGRST) to the AD converting part 430 via the connection node ND402.-
2.发明公开公开(公告)号：US20240365027A1
公开(公告)日：2024-10-31
申请号：US18646263
申请日：2024-04-25
发明人： Ryotaro HOTTA , Shunsuke OKURA , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N25/78 , H04N25/59 , H04N25/772 , H04N25/778
CPC分类号： H04N25/78 , H04N25/59 , H04N25/772 , H04N25/778
摘要： In a pixel signal processing part, a first input switch and an output switch are turned on and off in phase. When the first input switch and the output switch are ON and the second input switch is OFF, a first auto-zero switch and a second auto-zero switch are kept in the ON state to connect the second node to the reference potential (GND), so that a sampling capacitor, a feedback capacitor, and an auto-zero capacitor are operated in respective operation ranges of the capacitors, and the feedback capacitor is kept constant according to a difference of the input pixel signals, thereby making the output of the amplifier in linear response to the input signal.
-
3.发明公开公开(公告)号：US20230353898A1
公开(公告)日：2023-11-02
申请号：US18309400
申请日：2023-04-28
发明人： Kazuki TATSUTA , Shunsuke OKURA , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N25/65 , H04N25/78 , H04N25/77 , H01L27/146
CPC分类号： H04N25/65 , H04N25/78 , H04N25/77 , H01L27/14614 , H01L27/14616
摘要： A solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus are capable of reducing kTC noise of a LCG signal, preventing a drop in SNR at the conjunction point between a HCG signal and the LCG signal, and eventually achieving improved image quality. At a start of a reset period, first and second reset transistors are switched into a conduction state. During a predetermined first period after the reset period starts, the first reset line is kept connected to a reset potential. After the first period elapses, the second reset transistor is switched into a non-conduction state to switch the first reset line into a floating state, so that the first reset line has high impedance. After a second period elapses and when the reset period ends, the first reset transistor is switched into the non-conduction state.
-
公开(公告)号：US20230300497A1
公开(公告)日：2023-09-21
申请号：US17999693
申请日：2021-05-24
发明人： Masayuki UNO , Rimon IKENO , Ken MIYAUCHI , Kazuya MORI , Hideki OWADA
摘要： Some embodiments relate to an imaging system including an active pixel a comparator, a write control circuit, and an analog-to-digital conversion (ADC) memory. The active pixel may include a photodiode and a plurality of transistors. The comparator may be operative coupled to the active pixel and configured to receive an output of the active pixel. The write control circuit may be operative coupled to the comparator and configured to receive an output from the comparator. The ADC memory may be operatively coupled to the write control circuit. A data structure may be stored in the ADC memory, and may be configured to store at least a first data string, which may include a set of flag bits for identifying each ADC operation performed and a set of ADC data bits.
-
5.发明公开公开(公告)号：US20240022836A1
公开(公告)日：2024-01-18
申请号：US18221260
申请日：2023-07-12
发明人： Ken MIYAUCHI , Hideki OWADA , Kazuya MORI , Isao TAKAYANAGI
摘要： Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus that are capable of selecting a pixel operating mode between a RS mode and a GS mode and switching a conversion gain read-out mode, where signals produced with different conversion gains are read, among several options depending on a scene. As a result, the solid-state imaging device, the method for driving the solid-state imaging device and the electronic apparatus can minimize a drop in SNR at the conjunction point between a HCG signal and a LCG signal and also achieve high full well capacity and little dark noise. In a solid-state imaging device, a pixel part includes pixels arranged in a matrix pattern, and each pixel includes a photoelectric conversion reading part. The solid-state imaging device is capable of performing rolling shutter (RS) and global shutter (GS).
-
公开(公告)号：US20230300493A1
公开(公告)日：2023-09-21
申请号：US17999690
申请日：2021-05-24
发明人： Masayuki UNO , Rimon IKENO , Ken MIYAUCHI , Kazuya MORI , Hideki OWADA
IPC分类号： H04N5/225
CPC分类号： H04N25/77
摘要： Some embodiments relate to an active pixel for use in a digital pixel sensor (DPS) imaging system having complete intra-pixel charge transfer functionality. The active pixel may include a first photodiode, and a first transfer gate and a second transfer gate each operatively coupled to the first photodiode. The first transfer gate and the second transfer gate may reside at opposite sides of the first photodiode. An electron drift current within the first photodiode may cause two direction charge transfer of charge of the first photodiode to the first transfer gate and the second transfer gate.
-
公开(公告)号：US20230239594A1
公开(公告)日：2023-07-27
申请号：US17999682
申请日：2021-05-24
发明人： Masayuki UNO , Rimon IKENO , Ken MIYAUCHI , Kazuya MORI , Hideki OWADA
IPC分类号： H04N25/772 , H01L27/146
CPC分类号： H04N25/772 , H01L27/14612
摘要： Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.
-
8.发明申请公开(公告)号：US20220132067A1
公开(公告)日：2022-04-28
申请号：US17510891
申请日：2021-10-26
发明人： Kazuya MORI , Masayuki UNO , Hideki OWADA
IPC分类号： H04N5/378 , H04N5/3745 , H04N5/357 , H04N5/351
摘要： A photoelectric conversion reading part of a pixel includes a photoelectric conversion element for storing therein, in a storing period, charges generated by the photoelectric conversion, a transfer element for transferring, in a transfer period following the storing period, the charges stored in the photoelectric conversion element, an output node to which the charges stored in the photoelectric conversion element are transferred through the transfer element, a reset element for resetting, in a reset period, the output node to a predetermined potential, an output buffer part for converting the charges in the output node into a voltage signal at a level determined by the amount of the charges and outputting the voltage signal as the pixel signal, and an output voltage control part for controlling an output signal level of the pixel signal from the output buffer part to a controlled level determined by the operational state.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.019 秒)
