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1.发明公开公开(公告)号：US20240089635A1
公开(公告)日：2024-03-14
申请号：US18466486
申请日：2023-09-13
发明人： Isao TAKAYANAGI
IPC分类号： H04N25/771 , H04N25/60
CPC分类号： H04N25/771 , H04N25/60
摘要： Provided are a solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus that are capable of achieving reduced noise at a voltage sample-and-hold node without requiring an increase in capacitance of a signal holding capacitor for sampling and holding voltage. A solid-state imaging device includes: a photoelectric conversion reading part; an amplifier circuit; a signal holding part including a sample-and-hold signal holding capacitor for holding the read-out voltage signal amplified by the amplifier circuit and outputting the held voltage signal; a first in-pixel signal line to which a low-gain read-out voltage signal is output; and a second in-pixel signal line connected to the output side of the amplifier circuit and to which a high-gain read-out voltage signal is output. A second differential transistor of a differential transistor pair of the amplifier circuit also serves as a source follower transistor.
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2.发明申请公开(公告)号：US20220385852A1
公开(公告)日：2022-12-01
申请号：US17749404
申请日：2022-05-20
发明人： Ken MIYAUCHI , Isao TAKAYANAGI
IPC分类号： H04N5/3745 , H04N5/378 , H04N5/347 , H04N5/355
摘要： In a pixel 200, a floating diffusion FD11 and a first capacitor CS11 are selectively connected to each other via a first connection element LG11-Tr, to change the capacitance of the floating diffusion FD11 between a first capacitance and a second capacitance, thereby changing the conversion gain between a first conversion gain (HCG) corresponding to the first capacitance and a second conversion gain (MCG) corresponding to the second capacitance. The floating diffusion FD11 and a second capacitor CS12 are connected together through a second connection element SG11-Tr to change the capacitance of the floating diffusion FD11 to a third capacitance, thereby changing the conversion gain of the source following transistor SF11-Tr to a third conversion gain (LCG) corresponding to the third capacitance
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3.发明公开公开(公告)号：US20240196116A1
公开(公告)日：2024-06-13
申请号：US18553982
申请日：2022-04-04
发明人： Ken MIYAUCHI , Isao TAKAYANAGI , Kazuya MORI
IPC分类号： H04N25/771 , H04N23/667 , H04N25/51 , H04N25/57 , H04N25/63 , H04N25/76
CPC分类号： H04N25/771 , H04N23/667 , H04N25/51 , H04N25/57 , H04N25/63 , H04N25/7795
摘要： A pixel circuit 200 includes a readable pixel 210, a comparator 220, and a selector counter circuit 230. The readable pixel 210 performs photoelectric conversion at a photodiode PD11 and produces a readable signal corresponding to an illuminance condition of incident light. The readable pixel 210 includes an overflow path extending to a floating diffusion FD11. The comparator 220 compares a voltage signal (SFout) read out from the readable pixel 210 against a reference signal Vref and outputs a comparison result signal Vout indicating the result of the comparison. The selector counter circuit 230 includes a selector circuit for selecting an external clock or the output Vout from the comparator and a counter circuit for counting the output from the selector circuit.
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4.发明公开公开(公告)号：US20240089631A1
公开(公告)日：2024-03-14
申请号：US18466454
申请日：2023-09-13
发明人： Isao TAKAYANAGI
摘要： A solid-state imaging device includes: an output buffer part adapted to convert charge at an output node into a voltage signal corresponding to the amount of the charge, and output an active comparison result signal when the voltage signal and a first reference signal are the same level; an output buffer part adapted to convert the charge at the output node into a voltage signal corresponding to the amount of the charge, compare the voltage signal with the first reference signal, and output the active comparison result signal when the voltage signal and the first reference signal are the same level; the holding signal readout part disposed between the input node of the signal holding part and the feeding line of the second reference signal, conduction or non-conduction of the holding signal readout part being controlled depending on the comparison result signal outputted by the output buffer part.
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5.发明公开公开(公告)号：US20240022836A1
公开(公告)日：2024-01-18
申请号：US18221260
申请日：2023-07-12
发明人： Ken MIYAUCHI , Hideki OWADA , Kazuya MORI , Isao TAKAYANAGI
摘要： Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus that are capable of selecting a pixel operating mode between a RS mode and a GS mode and switching a conversion gain read-out mode, where signals produced with different conversion gains are read, among several options depending on a scene. As a result, the solid-state imaging device, the method for driving the solid-state imaging device and the electronic apparatus can minimize a drop in SNR at the conjunction point between a HCG signal and a LCG signal and also achieve high full well capacity and little dark noise. In a solid-state imaging device, a pixel part includes pixels arranged in a matrix pattern, and each pixel includes a photoelectric conversion reading part. The solid-state imaging device is capable of performing rolling shutter (RS) and global shutter (GS).
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6.发明申请公开(公告)号：US20220408047A1
公开(公告)日：2022-12-22
申请号：US17842279
申请日：2022-06-16
发明人： Shunsuke OKURA , Ai OTANI , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N5/378 , H04N5/355 , H04N5/363 , H04N5/3745
摘要： Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus capable of reading signals produced with different conversion gains and having different signal directions.
A pixel signal processing part 400 includes a first reading part 410 and a second reading part 420. Of a pixel signal PIXOUT input into an input node ND401, the first reading part 410 inverts the signal direction of a first-conversion-gain signal (HCGRST, HCGSIG) and outputs an inverted first-conversion-gain signal (HCGRST, HCGSIG), which has been subjected to inversion and amplification, to an AD converting part 430 via a connection node ND402. Of the pixel signal PIXOUT input into the input node ND401, the second reading part 420 keeps the signal direction of a second-conversion-gain signal (LCGSIG, LCGRST) unchanged, and outputs a non-inverted second-conversion-gain signal (LCGSIG, LCGRST) to the AD converting part 430 via the connection node ND402.-
7.发明公开公开(公告)号：US20240365027A1
公开(公告)日：2024-10-31
申请号：US18646263
申请日：2024-04-25
发明人： Ryotaro HOTTA , Shunsuke OKURA , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N25/78 , H04N25/59 , H04N25/772 , H04N25/778
CPC分类号： H04N25/78 , H04N25/59 , H04N25/772 , H04N25/778
摘要： In a pixel signal processing part, a first input switch and an output switch are turned on and off in phase. When the first input switch and the output switch are ON and the second input switch is OFF, a first auto-zero switch and a second auto-zero switch are kept in the ON state to connect the second node to the reference potential (GND), so that a sampling capacitor, a feedback capacitor, and an auto-zero capacitor are operated in respective operation ranges of the capacitors, and the feedback capacitor is kept constant according to a difference of the input pixel signals, thereby making the output of the amplifier in linear response to the input signal.
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8.发明公开公开(公告)号：US20230353898A1
公开(公告)日：2023-11-02
申请号：US18309400
申请日：2023-04-28
发明人： Kazuki TATSUTA , Shunsuke OKURA , Ken MIYAUCHI , Hideki OWADA , Sangman HAN , Isao TAKAYANAGI
IPC分类号： H04N25/65 , H04N25/78 , H04N25/77 , H01L27/146
CPC分类号： H04N25/65 , H04N25/78 , H04N25/77 , H01L27/14614 , H01L27/14616
摘要： A solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus are capable of reducing kTC noise of a LCG signal, preventing a drop in SNR at the conjunction point between a HCG signal and the LCG signal, and eventually achieving improved image quality. At a start of a reset period, first and second reset transistors are switched into a conduction state. During a predetermined first period after the reset period starts, the first reset line is kept connected to a reset potential. After the first period elapses, the second reset transistor is switched into a non-conduction state to switch the first reset line into a floating state, so that the first reset line has high impedance. After a second period elapses and when the reset period ends, the first reset transistor is switched into the non-conduction state.
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