公开(公告)号：US20140320229A1

公开(公告)日：2014-10-30

申请号：US13897314

申请日：2013-05-17

Applicant: Broadcom Corporation

Inventor： Tamer ALI

IPC: H03H11/30

CPC classification number: H03H11/30 ,  H03K19/018571 ,  H04L25/0298

Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.

Abstract translation: 提供包括配置为具有负载阻抗的输出的传输线驱动器。 传输线驱动器包括与输出串联耦合的上拉电路。 传输线驱动器还包括与输出串联耦合的下拉电路。 传输线驱动器包括具有可调阻抗的分流电路。 并联电路与输出端并联。 分流电路耦合到上拉电路和下拉电路。 分流电路被配置为接收分流控制信号以调节可调阻抗以提供对输出端的输出摆幅的线性控制。

公开(公告)号：US20150092829A1

公开(公告)日：2015-04-02

申请号：US14072641

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Tamer ALI ,  Hassan Maarefi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/0288 ,  H04L25/03885 ,  H04L2025/03471 ,  H04L2025/03681

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract translation: 用于信号的无源均衡和转换速率控制的装置包括第一分支，其包括与均衡电容器串联耦合的第一驱动器，以及包括与电阻器串联耦合的第二驱动器的第二分支。 第二分支可以与第一分支并联耦合，并且第一分支可以被配置为基于模式控制信号使能信号的无源均衡或转换速率控制之一。

公开(公告)号：US20150180649A1

公开(公告)日：2015-06-25

申请号：US14637306

申请日：2015-03-03

Applicant: BROADCOM CORPORATION

Inventor： Mahmoud Reza AHMADI ,  Siavash FALLAHI ,  Tamer ALI ,  Ali NAZEMI ,  Hassan MAAREFI ,  Burak CATLI ,  Afshin MOMTAZ

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract translation: 高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号，并产生多个具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。